AWR6843 datasheet(39/71 Pages) TI1

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AWR6843

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SWRS248 – APRIL 2020

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Specifications

(1)

The MASTER bit (SPIGCRx.0) is cleared ( where x = 0 or 1 ).

(2)

The CLOCK PHASE bit (SPIFMTx.16) is either cleared or set for CLOCK PHASE = 0 or CLOCK PHASE = 1 respectively.

(3)

tc(MSS_VCLK) = master subsystem clock time = 1 / f(MSS_VCLK). For more details, see the Technical Reference Manual.

(4)

When the SPI is in Slave mode, the following must be true: For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(MSS_VCLK) ≥ 25 ns, where

PS is the prescale value set in the SPIFMTx.[15:8] register bits.For PS values of 0: tc(SPC)S = 2tc(MSS_VCLK) ≥ 25 ns.

(5)

The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

5.10.3.3 SPI Slave Mode I/O Timings

Table 5-9. SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input,

and SPISOMI = output)(1)(2)(3)

NO.

PARAMETER

MIN

TYP

MAX

UNIT

tc(SPC)S

Cycle time, SPICLK(4)

2(5)

tw(SPCH)S

Pulse duration, SPICLK high (clock polarity = 0)

tw(SPCL)S

Pulse duration, SPICLK low (clock polarity = 1)

3(5)

tw(SPCL)S

Pulse duration, SPICLK low (clock polarity = 0)

tw(SPCH)S

Pulse duration, SPICLK high (clock polarity = 1)

4(5)

td(SPCH-SOMI)S

Delay time, SPISOMI valid after SPICLK high (clock

polarity = 0)

td(SPCL-SOMI)S

Delay time, SPISOMI valid after SPICLK low (clock

polarity = 1)

5(5)

th(SPCH-SOMI)S

Hold time, SPISOMI data valid after SPICLK high

(clock polarity = 0)

th(SPCL-SOMI)S

Hold time, SPISOMI data valid after SPICLK low

(clock polarity = 1)

4(5)

td(SPCH-SOMI)S

Delay time, SPISOMI valid after SPICLK high (clock

polarity = 0; clock phase = 0) OR (clock polarity = 1;

clock phase = 1)

td(SPCL-SOMI)S

Delay time, SPISOMI valid after SPICLK low (clock

polarity = 1; clock phase = 0) OR (clock polarity = 0;

clock phase = 1)

5(5)

th(SPCH-SOMI)S

Hold time, SPISOMI data valid after SPICLK high

(clock polarity = 0; clock phase = 0) OR (clock

polarity = 1; clock phase = 1)

th(SPCL-SOMI)S

Hold time, SPISOMI data valid after SPICLK low

(clock polarity = 1; clock phase = 0) OR (clock

polarity = 0; clock phase = 1)

6(5)

tsu(SIMO-SPCL)S

Setup time, SPISIMO before SPICLK low (clock

polarity = 0; clock phase = 0) OR (clock polarity = 1;

clock phase = 1)

tsu(SIMO-SPCH)S

Setup time, SPISIMO before SPICLK high (clock

polarity = 1; clock phase = 0) OR (clock polarity = 0;

clock phase = 1)

7(5)

th(SPCL-SIMO)S

Hold time, SPISIMO data valid after SPICLK low

(clock polarity = 0; clock phase = 0) OR (clock

polarity = 1; clock phase = 1)

th(SPCL-SIMO)S

Hold time, SPISIMO data valid after SPICLK high

(clock polarity = 1; clock phase = 0) OR (clock

polarity = 0; clock phase = 1)

AWR6843 Datasheet(PDF) 39 Page - Texas Instruments

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