AWR6843 datasheet(59/71 Pages) TI1

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AWR6843

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SWRS248 – APRIL 2020

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Detailed Description

6.3.4

Host Interface

The host interface can be provided through a SPI, UART, or CAN-FD interface. In some cases the serial

interface for automotive applications is transcoded to a different serial standard.

This device communicates with the host radar processor over the following main interfaces:

•

Reference Clock – Reference clock available for host processor after device wakeup

•

Control – 4-port standard SPI (slave) for host control. All radio control commands (and response) flow

through this interface.

•

Reset – Active-low reset for device wakeup from host

•

Host Interrupt - an indication that the mmwave sensor needs host interface

•

Error – Used for notifying the host in case the radio controller detects a fault

6.3.5

Master Subsystem Cortex-R4F

The master system includes an ARM Cortex R4F processor, clock with a maximum operating frequency of

200 MHz. User applications executing on this processor control the overall operation of the device,

including radar control through well-defined API messages, radar signal processing (assisted by the radar

hardware accelerator), and peripherals for external interfaces.

See the Technical Reference Manual for a complete description and memory map.

6.3.6

DSP Subsystem

The DSP subsystem includes TI’s standard TMS320C674x megamodule and several blocks of internal

memory (L1P, L1D, and L2). For complete information including memory map, please refer to Technical

Reference Manual.

6.3.7

Hardware Accelerator

The Radar Hardware Accelerator (HWA) is an IP that enables off-loading the burden of certain frequently

used computations in FMCW radar signal processing from the main processor. FMCW radar signal

processing involves the use of FFT and Log-Magnitude computations to obtain a radar image across the

range, velocity, and angle dimensions. Some of the frequently used functions in FMCW radar signal

processing can be done within the radar hardware accelerator, while still retaining the flexibility of

implementing other proprietary algorithms in the main processor. See the Radar Hardware Accelerator

User's Guide for a functional description and features of this module and see the Technical Reference

Manual for a complete list of register and memory map.

6.4

Other Subsystems

6.4.1

ADC Channels (Service) for User Application

The AWR6843 device includes provision for an ADC service for user application, where the

GPADC engine present inside the device can be used to measure up to six external voltages. The ADC1,

ADC2, ADC3, ADC4, ADC5, and ADC6 pins are used for this purpose.

•

ADC itself is controlled by TI firmware running inside the BIST subsystem and access to it for

customer’s external voltage monitoring purpose is via ‘monitoring API’ calls routed to the BIST

subsystem. This API could be linked with the user application running on the Master R4.

•

BIST subsystem firmware will internally schedule these measurements along with other RF and Analog

monitoring operations. The API allows configuring the settling time (number of ADC samples to skip)

and number of consecutive samples to take. At the end of a frame, the minimum, maximum and

average of the readings will be reported for each of the monitored voltages.

GPADC Specifications:

•

625 Ksps SAR ADC

•

0 to 1.8V input range

AWR6843 Datasheet(PDF) 59 Page - Texas Instruments

AWR6843 Datasheet(HTML) 59 Page - Texas Instruments

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