EM78P520N datasheet(36/124 Pages) EMC

36 / 124 page

EM78P520N

8-Bit Microprocessor with OTP ROM



Product Specification (V1.4) 04.08.2016

(This specification is subject to change without prior notice)

6.2.38

Bank 3 R6 URS (UART Status)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

URRD8

EVEN

PRE

PRERR

OVERR

FMERR

URBF

RXE

Bit 7 (URRD8): Receiving Data Bit 8

Bit 6 (EVEN):

Select Parity Check

0 : Odd parity

1 : Even parity

Bit 5 (PRE):

Enable Parity Addition

0 : Disable

1 : Enable

Bit 4 (PRERR): Parity Error Flag

Set to

“1” when parity error occurs and clear to “0” by software.

Bit 3 (OVERR): Over Running Error Flag

Set to

”1” when overrun error occurs and clear to “0” by software.

Bit 2 (FMERR): Framing Error Flag

Set to

“1” when framing error occurs and clear to “0” by software.

Bit 1 (URBF): UART Read Buffer Full Flag

Set to

“1” when one character is received. Reset to “0” automatically

when read from URS register. The URBF will be cleared by hardware

when enabling receiving. The URBF bit is read-only. Therefore,

reading the URS register is necessary to avoid overrun error.

Bit 0 (RXE):

Enable Receiving

0 : Disable

1 : Enable

6.2.39

Bank 3 R7 URRD (UART_RD Data Buffer)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

URRD7

URRD6

URRD5

URRD4

URRD3

URRD2

URRD1

URRD0

Bits 7~0 (URRD7~URRD0): UART Receive Data Buffer. Read only.

EM78P520N Datasheet(PDF) 36 Page - ELAN Microelectronics Corp

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