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EM78P520N Datasheet(PDF) 65 Page - ELAN Microelectronics Corp |
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EM78P520N Datasheet(HTML) 65 Page - ELAN Microelectronics Corp |
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65 / 124 page  EM78P520N 8-Bit Microprocessor with OTP ROM Product Specification (V1.4) 04.08.2016 57 (This specification is subject to change without prior notice) 6.8 Interrupt Registers for Interrupt R_BANK Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bank 0 0x0E IMR T1IE LVDIE ADIE SPIIE URTIE EXIE9 EXIE8 TCIE R/W R/W R/W R/W R/W R/W R/W R/W Bank 0 0x0F ISR T1IF LVDIF ADIF SPIIF URTIF EXIF9 EXIF8 TCIF R/W R/W R/W R/W R/W R/W R/W R/W Bank 1 0X0E EIMR EXIE7 EXIE6 EXIE5 EXIE4 EXIE3 EXIE2 EXIE1 EXIE0 R/W R/W R/W R/W R/W R/W R/W R/W Bank 1 0X0F EISR EXIF7 EXIF6 EXIF5 EXIF4 EXIF3 EXIF2 EXIF1 EXIF0 R/W R/W R/W R/W R/W R/W R/W R/W Bank 2 0X09 T2CR T2IF T2IE T2S T2MS1 T2MS0 T2P2 T2P1 T2P0 R/W R/W R/W R/W R/W R/W R/W R/W The EM78P520N has ten interrupt sources as listed below: TCC overflow interrupt External interrupt pin Watch timer interrupt Timer 1 overflow interrupt Timer 2 overflow interrupt A/D conversion complete interrupt UART transmit/receive/error interrupt SPI transmit/receive interrupt Low voltage detector This IC has internal interrupts which are falling edge triggered, namely: TCC timer overflow interrupt, and two 8-bit upper counter/timer overflow interrupt. If these interrupt sources change signal from high to low, the RF register will generate a “1” flag to the corresponding register if RE register is enabled. RF is the interrupt status register which records the interrupt request in flag bit. RE is the interrupt mask register. Global interrupt is enabled by ENI instruction and is disabled by DISI instruction. When one of the interrupts (when enabled) is generated, it will cause the next instruction to be fetched from Address 0003H~001BH according to the interrupt source. For EM78P520N, each individual interrupt source has its own interrupt vector as depicted in Table 7. Before the interrupt subroutine is executed, the contents of ACC, R3[4:0] and the R5 register will be saved by hardware. After the interrupt service routine is finished, ACC, R3[4:0] and R5 will be pushed back. While in interrupt service routine, other interrupt service routine should not be allowed to be executed, so if other interrupts occur in an interrupt service routine, the hardware will save this interrupt, after which when interrupt service routine is completed, the next interrupt service routine will be executed. |
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