EM78P520N datasheet(46/124 Pages) EMC

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EM78P520N

8-Bit Microprocessor with OTP ROM



Product Specification (V1.4) 04.08.2016

(This specification is subject to change without prior notice)

6.3 TCC/WDT Prescaler

Registers for the TCC/WDT Circuit

R_BANK Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 0

0X0D

TWTCR

WDTE WPSR2 WPSR1 WPSR0 TCCS

TPSR2 TPSR1 TPSR0

R/W

Bank 0

0x0E

IMR

T1IE

LVDIE

ADIE

SPIIE URTIE EXIE9 EXIE8

TCIE

R/W

Bank 0

0x0F

ISR

T1IF

LVDIF

ADIF

SPIIF URTIF EXIF9 EXIF8

TCIF

R/W

There are two 8-bit counters available as prescalers for the TCC and WDT, respectively.

The TPSR0~TPSR2 bits of the Bank 0 RD (TWTCR) register are used to determine the

ratio of the TCC prescaler. Likewise, the WPSR0~WPSR2 bits of the Bank 0 RD

(TWTCR) register are used to determine the WDT prescaler. The prescaler counter will

be cleared by the instructions each time they are written into TCC. The WDT and

prescaler

will be cleared by the “WDTC” and “SLEP” instructions. Figure 6-4 depicts the

circuit diagram of TCC/WDT.

R1 (TCC) is an 8-bit timer/counter. The TCC clock source can be internal clock main

clock or sub clock (32.768kHz). If TCC signal source is from the internal clock, TCC will

be incremented by 1 at every instruction cycle (without prescaler). As illustrated in

Figure 6-4. The watchdog timer is a free running on-chip RC oscillator. The WDT will

continue running even after the oscillator driver has been turned off (i.e. in sleep mode).

During normal operation or sleep mode, a WDT time-out (if enabled) will cause the

device to reset. The WDT can be enabled or disabled at any time during the normal

mode by software programming. Refer to WDTE bit of Bank 0 RD (TWTCR) register.

With no prescaler, the WDT time-out period is approximately 18 ms

Note: VDD=5V, Setup time period = 16.5ms ± 30%

VDD=3V, Setup time period = 18ms ± 30%

Setup time form the WDT.

EM78P520N Datasheet(PDF) 46 Page - ELAN Microelectronics Corp

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