8.2.2.2 Differential to Single-Ended Output Conversion

For systems using single-ended input ADCs to convert the analog output voltage into digital, Figure 8-3 shows

an example of a TLV6001 -based signal conversion and filter circuit. With R1 = R2 = R3 = R4, the output voltage

system and use NP0-type capacitors for best performance. For most applications, R1 = R2 = R3 = R4 = 10 kΩ

and C1 = C2 = 1000 pF yields good performance.

DCDC_OUT

DCDC_HGND

HLDO_IN

HLDO_OUT

HGND

INP

INN

NC

AMC3330

DCDC_IN

LDO_OUT

VDD

OUTP

OUTN

GND

DIAG

DCDC_GND

+

±

R4

R3

R1

R2

ADC

GND

GND

To MCU

C1

C2

GND

TLV6001

Figure 8-3. Connecting the AMC3330 Output to a Single-Ended Input ADC

For more information on the general procedure to design the filtering and driving stages of SAR ADCs, see the

18-Bit, 1MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise and 18-Bit Data

Acquisition Block (DAQ) Optimized for Lowest Power reference guides, available for download at www.ti.com.

8.2.3 Application Curve

Figure 8-4 shows the typical full-scale step response of the AMC3330

VIN

VOUTN

VOUTP

Figure 8-4. Step Respose of the AMC3330

8.3 What to Do and What Not to Do

Do not leave the analog inputs INP and INN of the AMC3330 unconnected (floating) when the device is powered

up on the high-side. If the device input is left floating, the bias current may generate a negative input voltage that

exceeds the specified input voltage range and the output of the device is invalid.

Connect the high-side ground (HGND) to INN, either directly or through a resistive path. A DC current path

between INN and HGND is required to define the input common-mode voltage. Take care not to exceed the input

common-mode range as specified in the Recommended Operating Conditions table.

AMC3330

SBASA34A – JUNE 2020 – REVISED OCTOBER 2020

www.ti.com

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