8.3.2 Pin Diagrams

Figure 8-6 shows the input structure for the logic level pins INHx, INLx. INHx and INLx has passive pull down, so

when inputs are floating the output of gate driver will be pulled low. Figure 8-7 shows the input structure for the

logic level pin inverted INLx. INLx in inverted mode has passive pull up, so when inputs are floating the output of

gate driver will be pulled low.

INHx

INLx

Logic High

INPUT

Logic Low

200 k

Figure 8-6. INHx and non-inverted INLx Logic-Level

Input Pin Structure

INLx

Logic High

INPUT

Logic Low

200 k

INT_5V

Figure 8-7. Inverted INLx Logic-Level Input Pin

Structure

8.3.3 Gate Driver Protective Circuits

The DRV8300 is protected against BSTx undervoltage and GVDD undervoltage events.

Table 8-1. Fault Action and Response

FAULT

CONDITION

GATE DRIVER

RECOVERY

(BSTUV)

GHx - Hi-Z

Automatic:

PWM edge detected on INHx pin

GVDD undervoltage

(GVDDUV)

Hi-Z

Automatic:

The DRV8300 has separate voltage comparator to detect undervoltage condition for each phase. If at any time

particular phase is disabled by disabling (Hi-Z) GHx pin. Normal operation starts again when the BSTUV

condition clears and low to high PWM edge detected on INHx input on the same phase BSTUV was detected.

BSTUV protection ensures that high side gate driver are not switched when BSTx pin has lower value.

8.3.3.2 GVDD Undervoltage Lockout (GVDDUV)

MOSFETs are disabled. Normal operation starts again GVDDUV condition clears. GVDDUV protection ensures

that gate driver are not switched when GVDD input is at lower value.

8.4 Device Functional Modes

gate driver output GHx and GLX will follow respective inputs INHx and INLx.

www.ti.com

DRV8300

SLVSFG5 – SEPTEMBER 2020

Copyright © 2020 Texas Instruments Incorporated

Submit Document Feedback

15

Product Folder Links: DRV8300