LTC3370 datasheet(17/28 Pages) AD

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LTC3376

Rev 0

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OPERATION

Buck Switching Regulators

TheLTC3376isa20Vmonolithic,constantfrequency,four

channel, 12A configurable, peak current mode step-down

DC/DC converter. The device includes four synchronous

buck converters, configured to share eight 1.5A power

stages. The LTC3376 includes the integration of ceramic

capacitors into the package for all BST pins. These capaci-

tors reduce PC board space by eliminating the need for

external BST capacitors.

The buck switching regulators are internally compensated

and require external feedback resistors to set the output

voltage. An internal oscillator, which can be synchronized

to an external oscillator, turns on the internal top power

switch at the beginning of each clock cycle. Current in the

inductor ramps up until the top switch current comparator

trips and turns off the top power switch. The peak inductor

current at which the top switch turns off is controlled by

an internal VC voltage which the error amplifier regulates

by comparing the voltage on the feedback pin with an in-

ternal 400mV reference. When the load current increases,

it causes a reduction in the feedback voltage relative to the

referencecausingtheerroramplifiertoraisetheVCvoltage

until the average inductor current matches the new load

current. When the top power switch turns off, the bottom

power switch turns on until the next clock cycle begins or,

if in Burst Mode, until the inductor current falls to zero.

Each buck converter can operate at an independent VIN

voltage and has its own FB+, FB–, RUN, IMON, and PGOOD

pins to maximize flexibility. The RUN pins have two differ-

ent enable threshold voltages that depend on the operating

state of the LTC3376. The first buck regulator to turn on

will have a RUN pin rising threshold of 730mV(typ). The

last buck regulator to turn off will have a RUN pin falling

threshold of 690mV(typ). If any one buck regulator is on,

all other RUN pins will use the bandgap-based precision

thresholds off 300mV(typ) rising and 200mV(typ) falling.

The precision RUN thresholds may be used to provide

event-based power-up sequencing by connecting the RUN

pin to the output of another buck through a resistor divider.

All buck regulators have forward and reverse-current limit-

ing, short-circuit protection, and soft-start to limit inrush

current during start-up. If the RUN pin of a buck is low, that

buck is shut down to a low quiescent current state and the

SW pin is pulled to PGND through a 1k resistor. If all buck

regulatorsareoff,mosttoplevelcircuitsareshutdown,and

the quiescent current of the LTC3376 is 9µA(typ). When a

buck is enabled there is a 100μs(typ) delay before switch-

ing commences and the soft start ramp begins. If a buck

is the first one to be enabled, then this delay is 250µs(typ).

The buck switching regulators are phased in 90° steps to

reduce noise and input ripple. The phase step determines

the fixed edge of the switching sequence, which is when

the top switch turns on. The top switch off (bottom switch

on) phase is subject to the duty cycle demanded by the

regulator. Buck 2 is set to 0°. Buck 1 is set to 90°. Buck 4

is set to 180°. Buck 3 is set to 270°.

Buck Regulators with Combined Power Stages

Up to four buck regulators may be combined in a master-

slave configuration in various combinations by setting the

CFG0, CFG1, CFG2, and CFG3 pins. These configuration

pins should either be tied to ground or tied to INTVCC in

accordance with the desired configuration (Table 1). Any

combined SW pins must be tied together, as must any of

the combined VIN and BST pins. The bucks have a com-

mon VINbuteachVINpinshouldhaveitsowninputbypass

capacitors (see Applications Information). RUN1, FB1+,

FB1–, IMON1, and PGOOD1 are utilized by Buck 1. RUN2,

FB2+, FB2–, IMON2, and PGOOD2 are utilized by Buck 2.

RUN3,FB3+,FB3–,IMON3,andPGOOD3areutilizedbyBuck

3. RUN4, FB4+, FB4–, IMON4, and PGOOD4 are utilized by

Buck 4. If a buck is not utilized in a particular configuration,

then the RUN, FB+, and FB–, IMON, PGOOD pins should

be tied to GND. Its VIN, SW, and BST pins will be used as

a slave to another master and must be connected to that

master’s respective power pins.

Buck regulators can be combined to provide 3A, 4.5A, 6A,

7.5A,9A,10.5A,or12Aofoutputloadcurrent.Forexample,

code 0110 (CFG[3:0]) configures Buck 1 to operate as a

4.5A regulator through VIN/SW/BST pairs A, B, and H,

while Buck 2 is disabled, Buck 3 operates as a 6A regula-

tor through VIN/SW/BST pairs C, D, E, and F, and Buck 4

operates as a 1.5A regulator through VIN/SW/BST pair G.

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