LTC3370 datasheet(18/28 Pages) AD

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LTC3376

Rev 0

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OPERATION

Table 1. Master-Slave Program Combinations

(Each Letter Corresponds to a VIN/SW/BST/PGND Pair)

OUTPUT CONFIGURATION

CFG3 CFG2 CFG1 CFG0

BUCK 1

BUCK 2 BUCK 3 BUCK 4

ABH

CDE

ABDH

CDE

FGH

ABCD

ABH

CDEF

ABCD

EFGH

ABDEH

ABCDH

ABCDE

FGH

ABCDEH

ABCDEF

ABCDEFH

ABCDEFGH

Mode Selection

The buck switching regulators can operate in two different

modes set by the SYNC/MODE pin: Burst Mode (when

the SYNC/MODE pin is set low) and forced continuous

PWM mode (when the SYNC/MODE pin is set high). The

SYNC/MODE pin sets the same operating mode for all

buck switching regulators.

Inforcedcontinuousmode,theoscillatorrunscontinuously

and the buck switch currents are allowed to reverse under

light load conditions to maintain regulation. This mode

allows the buck to run at a fixed frequency with minimal

output ripple, even with zero output load.

InBurstModeoperation,atlightloadstheoutputcapacitor

is charged to a voltage slightly higher than its regulation

point. The regulator then goes into a sleep state, during

which time the output capacitor provides the load current.

In sleep most of the regulator’s circuitry is powered down,

helping conserve input power. When the output capacitor

dropsbelowitsprogrammedvalue,thecircuitryispowered

onandanotherburstcyclebegins.Thesleeptimedecreases

as load current increases. In Burst Mode operation, the

regulator will burst only at light loads. At higher loads it

will operate in constant frequency PWM mode.

Synchronizing the Oscillator to an External Clock

Selection of the operating frequency is a trade-off between

efficiency and component size. High frequency operation

allows the use of smaller inductor and capacitor values

and improves transient response. Operation at lower

frequencies improves efficiency by reducing internal gate

charge losses and allows more extreme VIN to VOUT ratios.

However, this also requires larger inductance values and/

or capacitance to maintain low output voltage ripple. The

LTC3376 has a default operating frequency of 2MHz.

The LTC3376’s internal oscillator can alternatively be

synchronized through an internal PLL circuit to an external

frequency by applying a square wave clock signal to the

MODE/SYNC pin. During synchronization, the top power

device turn-on of buck 2 is locked to 110ns after the ris-

ing edge of the external frequency source. Buck 1 will be

90° out of phase with Buck 2. Buck 4 will be 180° out of

phase with Buck 2. Buck 3 will be 270° out of phase with

Buck 2. When synchronizing to an external clock, the

buck regulators operate in forced continuous mode. The

synchronization frequency range is 1MHz to 3MHz.

After detecting an external clock on the first rising edge

of the SYNC pin, the internal PLL starts at the default

frequency. The internal PLL then requires up to 1ms to

gradually adjust its operating frequency to match the

frequency and phase of the SYNC signal.

WhentheexternalclockisremovedtheLTC3376willdetect

the absence of the external clock, and the oscillator gradu-

ally adjusts its operating frequency back to the default.

Power Failure Reporting Via PGOOD Pins

Power failure conditions are reported back by each buck’s

associated PGOOD pin. Each buck switching regulator has

an internal power good (PGOOD_INT) signal. When the

regulatedoutputvoltageofanenabledswitcherrisesabove

97.75% of its regulation output voltage the PGOOD_INT

signal transitions high. If the regulated output voltage

subsequently falls below 96.75%(typ) of the regulation

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