AP0201AT

www.onsemi.com

4

SYSTEM INTERFACES

Figure 3 shows typical AP0201AT device connections.

All power supply rails must be decoupled from ground

using capacitors as close as possible to the package.

The AP0201AT signals to the sensor and host interfaces

can be at different supply voltage levels to optimize power

consumption and maximize flexibility. Table 3 on page 5

provides the signal descriptions for the AP0201AT.

GND

Sensor IO

power

1.8 V

(Regulator IP)

1.2 V (Regulator OP)

Power up Core and PLL

PHY

power

OTP

power

HOST IO

power

OR

VDDIO_S

EXTCLK_OUT

RESET_BAR_OUT

FV_IN

LV_IN

PIXCLK_IN

DIN[11:0]

HISPICN

HISPICP

HISPI0N

HISPI0P

HISPI1N

HISPI1NP

TRIGGER_OUT

EXTCLK

STANDBY

TRST_BAR

RESET_BAR

FRAME_SYNC

XTAL

PHY_RESET_BAR

SPI_CS_BAR

GTX_CLK

SPI_SDO

SPI_SDI

GPIO[6:0]

EXT_REG

RESERVED[1:0]

MDC

MDIO

TX_CLK

TX_EN

TXD[7:0]

TX_ERR

RX_CLK

CRS_DV

RX_ERR

RXD[7:0]

(Note 6)

(Note 4)

LDO_OP

(Note 4)

NOTES: 1. This typical configuration shows only one scenario out of multiple possible variations for this device.

3. RESET_BAR has an internal pull−up resistor and can be left floating if not used.

4. The decoupling capacitors for the regulator input and output should have a value of 1.0 mF. The capacitors should be ceramic

and need to have X5R or X7R dielectric.

5. TRST and RESERVED[0] connect to GND for normal operation, RESERVED[3:2] are floating and RESERVED[1] is connected

to VDDIO_H for normal operation.

6. ON Semiconductor recommends that 0.1 mF and 1 mF decoupling capacitors for each power supply are mounted as close as

possible to the pin. Actual values and numbers may vary depending on layout and design consideration.

Figure 3. Typical Ethernet Configuration

Ethernet MAC Signals