AP0201AT datasheet(27/31 Pages) ONSEMI

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AP0201AT

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Input Clocks

Table 17. INPUT CLOCKS

Clock

Min (MHz)

Typical (MHz)

Max (MHz)

Description

EXTCLK

10 − osc

20 − xtal

Primary system clock. Drives PLLs. Crystal frequency range is

20 − 29 MHz, otherwise 10 − 29 MHz.

PIXCLK_IN

74.25

Clock for parallel input bus (from sensor).

HISPI_CLK

300

Clock for HISPI image data receiver.

Output Clocks

Table 18. OUTPUT CLOCKS

Clock

Min (MHz)

Typical (MHz)

Max (MHz)

Description

MCLK

Primary clock to sensor. Equals EXTCLK.

GTX_CLK

74.25/25

80/125

Clock of parallel output bus.

If pad voltage is 1.8 V nominal, then max frequency is 80 MHz.

If 2.5 V or 3.3 V, then 125 MHz. See electrical specs.

SPI_CLK

SPI clock to nonvolatile external memory.

Figure 16. Frame_Sync Diagram

FRAME_SYNC

TRIGGER_OUT

FV_OUT

t_FRAMESYNC

t_TRIGGER_PROP

t_FRMSYNC_FVH

Table 19. TRIGGER TIMING

Parameter

Name

Conditions

Min

Typ

Max

Unit

FRAME_SYNC to FV_OUT

tFRMSYNC_FVH

8 lines + exposure

time + sensor delay

−

Lines

FRAME_SYNC to

TRIGGER_OUT

tTRIGGER_PROP

−

tFRAME_SYNC

tFRAMESYNC

−

EXTCLK

cycles

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