AP0201AT datasheet(8/31 Pages) ONSEMI

8 / 31 page

AP0201AT

www.onsemi.com

POWER−UP SEQUENCE

Powering up the AP0201AT requires voltages to be

applied in a particular order, as seen in Figure 5. The timing

requirements are shown below. The AP0201AT includes a

power−on reset feature that initiates a reset upon power up.

dv/dt

VDDIO_H

VDD_REG

EXTCLK

SCLK

SDATA

VDDIO_S, VDDIO_OTPM,

VDD_PHY(when using HiSPi)

dv/dt

Figure 5. Power−Up and Power−Down Sequence

Table 6. POWER−UP AND POWER−DOWN SIGNAL TIMING

Symbol

Parameter

Min

Typ

Max

Unit

Delay from VDDIO_H to VDDIO_S, VDDIO_OTPM, VDD_PHY

(when using HiSPi)

−

Delay from VDDIO_H to VDD_REG

−

EXTCLK activation

t2+1

−

First serial command (Note 4)

100

−

EXTCLK cycles

EXTCLK cutoff

−

Delay from VDD_REG to VDDIO_H

−

Delay from VDDIO_S, VDDIO_OTPM, VDD_PHY (when using

HiSPi) to VDDIO_H

−

dv/dt

Power supply ramp time (slew rate)

−

0.1

V/ms

4. When using XTAL the settling time should be taken into account.

RESET AND STANDBY MODES

Reset

The AP0201AT has three types of reset available:

• A hard reset is issued by toggling the RESET_BAR

signal.

• A soft reset is issued by writing commands through

the Ethernet interface.

• An internal power−on reset.

Table 7 shows the output states when the part is in various

states.

Table 7. OUTPUT STATES

Name

Hardware States

Firmware States

Notes

Reset State

Default

State

Hard

Standby

Soft

Standby

Streaming

Idle

EXTCLK

(clock running

or stopped)

(clock running)

(clock running

or stopped)

(clock running)

Input

XTAL

n/a

Output

RESET_BAR

(asserted)

(negated)

Input

AP0201AT Datasheet(PDF) 8 Page - ON Semiconductor

AP0201AT Datasheet(HTML) 8 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Datasheet Download

Link URL