F4482 Datasheet

© 2020 Renesas Electronics Corporation

37

December 15, 2020

Table 9 represents the truth table for the attenuator control bits. A full scale DSA setting of 000000 drives the channel DSA into its minimum

attenuation state. Conversely, a setting of 111111 drives the channel DSA into its maximum attenuation state. Note that D5 is defined as the

Most Significant Bit (MSB) for the attenuator control function within each respective channel.

Table 9. DVGA Attenuation Word Truth Table

Attenuation

Setting (dB)

Reserve

Control Bits

D7

D6

D5

D4

D3

D2

D1

D0

0.0

X

X

0

0

0

0

0

0

0.5

X

X

0

0

0

0

0

1

1.0

X

X

0

0

0

0

1

0

2.0

X

X

0

0

0

1

0

0

4.0

X

X

0

0

1

0

0

0

8.0

X

X

0

1

0

0

0

0

16.0

X

X

1

0

0

0

0

0

31.5

X

X

1

1

1

1

1

1

It should also be noted that the listing above represents an abbreviated version of the complete 6-bit attenuator control truth table. Any attenuator

combination of 0.5dB, 1dB, 2dB, 4dB, 8dB, and 16dB can be achieved by simply assigning a logic HIGH in the respective control bit. For

instance, to achieve an attenuation setting of 21.5dB within a given channel, assign a logic HIGH to bits D0, D1, D3, and D5 while assigning a

logic LOW to bits D2 and D4. Doing so selects a combination of 0.5dB (D0) + 1dB (D1) + 4dB (D3) + 16dB (D5) = 21.5dB. Setting all of the

control bits to logic HIGH will step in all of the attenuator stages.