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F4482 Datasheet(PDF) 1 Page - Renesas Technology Corp |
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F4482 Datasheet(HTML) 1 Page - Renesas Technology Corp |
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1 / 49 page  DIFF-In / SE-Out Quad Path TX DVGA 1300MHz to 2800MHz F4482 Datasheet © 2020 Renesas Electronics Corporation 1 December 15, 2020 Description The F4482 is a 1300MHz to 2800MHz Quad Path TX DVGA outfitted with 100Ω differential inputs and 50Ω single-ended outputs. The device is part of a complete family of VGAs targeting FDD and TDD applications within the 400MHz to 4200MHz frequency range. Using a single 3.3V power supply and only 500mA of ICC, the F4482 provides four independent transmit paths, each with 28dB typical maximum gain, +34dBm OIP3, +17dBm output P1dB, and 5.7dB NF. Each channel includes a glitch-free digital step attenuator that reduces gain by up to 31.5dB in precise 0.5dB steps. The F4482 is packaged in an 8 × 8 mm 56-LGA, with matched 100Ω differential input and 50Ω single-ended output impedances for ease of integration into the signal path. Competitive Advantage Combines four independent TX channels consisting of an LPF, LNA, DSA, and Driver in a compact 8 × 8 LGA package Low DC power High linearity High reliability Uses Renesas’ patented Zero-DistortionTM and Glitch-FreeTM technologies, providing superior performance and PA damage protection over the entire RF gain range Typical Applications 4G and 5G Multi-mode, Multi-carrier Transmitters LTE and UMTS/WCDMA Base Stations Active Antenna Systems Digital Radio Features Independent Quad Channels for FDD TX applications RF Range: 1300MHz to 2800MHz • F4481: 400MHz to 1100MHz 28dB Typical Maximum Gain at 2100MHz Precise SPI-Controlled Glitch-FreeTM Gain Adjustment • 31.5dB Gain Range with 0.5dB Step Size 5.7dB NF at 2100MHz +34dBm OIP3 at 2100MHz +17dBm Output P1dB at 2100MHz 3.3V Supply Voltage ICC = 500mA 100Ω Differential Input Impedances 50Ω Single-ended Output Impedances 1.8V and 3.3V Logic Support Independent Channel Standby Modes for Power Savings Operating Temperature (TEP) Range: -40°C to +105°C 8 × 8 mm, 56-LGA package Block Diagram |
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