F4482 Datasheet

© 2020 Renesas Electronics Corporation

13

December 15, 2020

Parameter

Symbol

Condition

Minimum

Typical

Maximum

Units

Serial Clock Speed

50

MHz

CSb to First Serial Clock Rising Edge

SPI 3 wire bus. 50% of CSb

falling edge to 50% of CLK rising

edge

10

ns

Serial Data Hold Time

SPI 3 wire bus. 50% of CLK

rising edge to 50% of DATA

falling edge

10

ns

Final Serial Clock Rising Edge to CSb

SPI 3 wire bus. 50% of CLK

rising edge to 50% of CSb rising

edge

10

ns

Stability K Factor

10MHz to 9GHz

1

[a] Specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. Specifications in these columns that are

not shown in bold italics are confirmed by design characterization.

[b] For input signal power level equal to P1dB, expect DC current to increase above typical value.

[c] Timing is measured after SPI programming is completed (data latched with CSb = HIGH).