F4482 datasheet(11/49 Pages) RENESAS

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F4482 Datasheet

December 15, 2020

Electrical Characteristics – General

See the F4482 Typical Application Circuit. Unless stated otherwise, specifications apply when operated with VCC = +3.3V, TEP = +25°C,

fRF = 2100MHz, STBY_A = STBY_B = STBY_C = STBY_D = HIGH, ZS = 100Ω differential, ZL = 50Ω single-ended, maximum gain setting,

and output power = 0dBm/tone. EVKit trace and connector losses are de-embedded.

Table 4. Electrical Characteristics – General

Parameter

Symbol

Condition

Minimum

Typical

Maximum

Units

Logic Input HIGH

VIH

Supports both 1.8V and 3.3V

logic

1.07 [a]

Logic Input LOW

VIL

0.63

SPI Logic Current

(CSb, CLK, DATA)

ICTL

3.3V Logic

-5

µA

1.8V Logic

-5

Standby Logic Current

(STBY_A, STBY_B, STBY_C,

STBY_D)

IIH, IIL

3.3V Logic

µA

1.8V Logic

Supply Current [b]

ICC_4

Four channels on

490

600

ICC_3

Three channels on

374

ICC_2

Two channels on

252

ICC_1

One channel on

135

Standby Current

ICC_STBY

All channels off

Power ON Switching Time

tON

50% STBY to RF output settled

to within ±0.5dB

µs

Power OFF Switching Time

tOFF

50% STBY to 35 dBc reduction

of output power

µs

Lineup Out-of-Band Rejection at

Max Gain

fREJECTION

Total gain variation over

fRF = 1300MHz to 1700MHz.

Referred to fRF = 1450MHz.

DSA 0dB attenuation.

dBc

Total gain variation over

fRF = 1700MHz to 2800MHz.

Referred to fRF = 2100MHz.

DSA 0dB attenuation.

6GHz < fRF < 11.75GHz.

Referred to fRF = 2100MHz.

DSA 0dB attenuation.

Gain Settling Time [c]

GST

Any 2dB step in the 0dB to

31.5dB range. 50% of CSb to

1% / 99% RF.

0.4

µs

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