F4482 Datasheet

© 2020 Renesas Electronics Corporation

39

December 15, 2020

SPI Timing Intervals

Figure 79 shows the relevant SPI timing intervals which are specified in Table 10.

Note: The F4482 includes a CLK inhibit feature designed to minimize sensitivity to CLK bus noise when the device is not being programmed.

Table 10. SPI Timing Diagram Values for the Serial Mode

Parameter

Symbol

Test Condition

Minimum

Typical

Maximum

Units

CLK Frequency

20

MHz

CLK High Duration Time

20

ns

CLK Low Duration Time

20

ns

DATA to CLK Setup Time

10

ns

40

ns

CLK to DATA Hold Time

10

ns

Final CLK Rising Edge to CSb Rising

Edge

10

ns

CSb to CLK Setup Time

10

ns

CSb Trigger Pulse Width

10

ns

10

ns

MSB

LSB

Time

CLK

DATA

CSb