LTC4449 datasheet(27/48 Pages) AD

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LTC7871

Rev. 0

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of 4.7μF ceramic capacitor or low ESR electrolytic capaci-

tor. No matter what type of bulk capacitor is used, an addi-

tional 0.1μF ceramic capacitor placed directly adjacent to

the V5 and SGND pins is highly recommended.

Fault Conditions: Current Limit and Current Foldback

In buck mode, the LTC7871 includes current foldback to

help limit power dissipation when the VLOW is shorted to

ground. If the VLOW falls below 33% of its nominal output

level, then the maximum sense voltage is progressively

lowered from its maximum programmed value to one-third

of the maximum value. Foldback current limiting is disabled

during soft-start. Under short-circuit conditions with very

low duty cycles, the LTC7871 will begin cycle skipping in

order to limit the short-circuit current. In this situation the

bottom MOSFET will be dissipating most of the power but

less than in normal operation. The short circuit ripple cur-

rent is determined by the minimum on-time tON(MIN) of the

LTC7871, the VHIGH voltage and inductor value:

∆IL SC

( ) = tON MIN

(

) •

VHIGH

The resulting short circuit current is:

ISC =

3 VSENSE MAX

(

)

RSENSE

–

∆IL SC

( )

⎛

⎝⎜

⎞

⎠⎟

After a short, make sure that the load current takes the

folded back current limit into account.

Phase-Locked Loop and Frequency Synchronization

The LTC7871 has a phase-locked loop (PLL) comprised

of an internal voltage-controlled oscillator (VCO) and a

phase detector. This allows the turn-on of the top MOSFET

to be locked to the rising edge of an external clock signal

applied to the SYNC pin. The phase detector is an edge

sensitive digital type that provides zero degrees phase

shift between the external and internal oscillators. This

type of phase detector does not exhibit false lock to har-

monics of the external clock.

The output of the phase detector is a pair of comple-

mentary current sources that charge or discharge the

internal filter network. There is a precision 20μA current

External Soft-Start

The LTC7871 has the ability to soft-start by itself using

the internal soft-start or at a slower rate with an external

capacitor on the SS pin. The controller is in the shutdown

state if its RUN pin voltage is below 1.14V and its SS pin

is actively pulled to ground in this shutdown state. If the

RUN pin voltage is above 1.22V, the controller powers

up. Once V5 and DRVCC pass the UVLO thresholds and

power on reset delay expires, a soft-start current of 1μA

then starts to charge the SS soft-start capacitor. Note that

soft-start is achieved not by limiting the maximum VLOW

output current of the controller but by controlling the out-

put ramp voltage according to the ramp rate on the SS

pin. Current foldback is disabled during this phase. The

soft-start range is defined to be the voltage range from

0V to 1.2V on the SS pin. The total soft-start time can be

calculated as:

tSOFTSTART = 1.2 •

CSS

1µA

The Internal LDOs

The LTC7871 features three internal PMOS LDOs. Two

provide power to DRVCC from either the VHIGH or VLOW

supply, and the third provides the V5 rail from DRVCC.

DRVCC powers the external top and bottom gate drive

circuits, and V5 powers the LTC7871’s internal circuitry.

There are two DRVCC LDOs—one that converts DRVCC

from VHIGH (LDO1) and another that converts DRVCC from

VLOW (LDO2), thus allowing the part to start up with just

one of the two rails present! Only one of those LDOs is

active at any given time. If VLOW is higher than the EXTVCC

switchover threshold, LDO2 is active; if it is below the swi-

tchover threshold, LDO1 is active. The DRVCC pin regula-

tion voltage is determined by the state of the DRVSET pin.

The DRVSET pin uses a 3-level logic. When DRVSET is

either grounded, floated or tied to V5, the typical value for

the DRVCC voltage will be 5V, 8V and 10V, respectively.

Please note that the DRVSET pin has an internal 160kΩ pull

down resistor to SGND and a 200kΩ pull up resistor to V5.

The V5 LDO regulates the voltage at the V5 pin to 5V when

DRVCC is at least 6V. The LDO can supply a peak current of

20mA and must be bypassed to ground with a minimum

APPLICATIONS INFORMATION

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