ADL5206

Data Sheet

Rev. 0 | Page 6 of 25

TIMING SPECIFICATIONS

Table 2. SPI Timing Parameters

Parameter

Description

Min Typ

Max Unit

25

MHz

Minimum period that SCLK is in a logic high state

10

ns

Minimum period that SCLK is in a logic low state

10

ns

Setup time between the data and the rising edge of SCLK

5

ns

Hold time between the data and the rising edge of SCLK

5

ns

Setup time between the falling edge of CS and the rising edge of SCLK

10

ns

Hold time between the rising edge of CS and the last falling edge of SCLK

10

ns

Maximum time delay between the falling edge of SCLK and the output data valid for a read

operation

5

14

ns

Maximum time delay between CS deactivation and the SDIO bus return to high impedance

12

ns

Timing Diagrams

R/W

A3

A2

A1

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

A7

A6

A5

A4

A8

A13 A12

A14

ADDRESS

A11 A10 A9

SCLK

CS

SDI

Figure 2. SPI Register Timing, MSB First

CS

SCLK

SDI

R/W

CS5

CS4

0

A2

A1

A_LSB

D_MSB

D6

D5

D1

D_LSB

A7

A_MSB

0

0

0

Figure 3. Timing Diagram for the SPI Register Write

SCLK

CS

SDIO

R/W

A2

A1

A_LSB

A7

D_MSB

D6

D5

D1

D_LSB

A_MSB

A8

A12

A13

A9

A11

A10

Figure 4. Timing Diagram for SPI Register Read