Data Sheet

ADL5206

Rev. 0 | Page 9 of 25

Pin No.

Mnemonic

Description

11

LATCH/SPI_HP_LP

The latch when the MODE0 and MODE1 pins are in parallel mode (LATCH). A logic low on this pin

allows the gain to change, and a logic high on this pin prevents the gain change. In SPI mode, logic

high selects high performance mode, and logic low selects low power mode (SPI_HP_LP).

13

PWUP

Power-Up. PWUP remains the power-up pin function with any selection of the MODE0 and MODE1

pins. A logic high on this pin powers up, and a logic low on this pin powers down.

14

VOUT−

Negative Analog Output.

15

VOUT+

Positive Analog Output.

16, 19

VPOS

Positive Power Supply, 5 V.

17

VIN+

Positive Analog Input.

18

VIN−

Negative Analog Input.

20

DNC INTERIM

Do Not Connect. Tie DNC INTERIM to a resistor divider that is 25 kΩ to 5 V and 50 kΩ to ground or to

a pull-up that is 50 kΩ to 3.3 V.

EP

Exposed Pad Ground. The exposed pad must be connected to a low impedance ground plane. This

plane is the ground (0 V) reference for all voltages in Table 1.

Table 6. Pin Function Overview for Various Modes

Mode

Pin 2

Pin 3

Pin 4

Pin 5

Pin 6

Pin 7

Pin 8

Pin 9

Pin 11

Pin 13

Parallel

High Performance

0

0

Unused

D4

D3

D2

D1

D0

LATCH

1

Low Power

1

1

Unused

D4

D3

D2

D1

D0

LATCH

1

SPI, 3-Wire

High Performance

0

1

SDIO

SCLK

CS

FA

Unused

0

0

1

Low Power

0

1

SDIO

SCLK

CS

FA

Unused

0

1

1

SPI, 4-Wire

High Performance

0

1

SDO

SCLK

CS

FA

SDI

1

0

1

Low Power

0

1

SDO

SCLK

CS

FA

SDI

1

1

1

Up or Down

High Performance

1

0

Unused

Unused

GS1

GS0

UPDN_CLK

UPDN_DAT

0

1

Low Power

1

0

Unused

Unused

GS1

GS0

UPDN_CLK

UPDN_DAT

1

1