ADL5206ACPZ-R7 datasheet(23/25 Pages) AD

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Data Sheet

ADL5206

Rev. 0 | Page 23 of 25

Table 12. Gain Code vs. Voltage Gain

5-Bit Binary Gain Code, D4 to D0

Voltage Gain (dB)

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

SPI READ

The ADL5206 can be read back only in serial mode during a

read cycle (from CS low to CS high) after the R/W bit is set high

in the previous cycle. During the read cycle, data changes at

each rising edge of SCLK and can be latched using the falling

edge of SCLK. There is no continual read operation. A logic

high (1) must be written into the R/W bit to enable the subsequent

read cycle, and once the R/W bit is set, the rest of the bits are

ignored in that write cycle.

The sequence for writing and then reading back is shown in

Figure 60 to Figure 62, showing the operation of the input and

output functions of the SDIO pin.

SCLK

WRITE VALUE

WRITE 0x54

R/W BIT LOW ON SDIO (IN)

DATA WRITTEN ON RISING CLOCK EDGE

SDIO (IN)

SDIO (OUT)

Figure 60. Write Gain Control Word

SET UP READ

WRITE 0x10

R/W BIT LOW ON SDIO (OUT)

SDIO (IN)

SCLK

SDIO (OUT)

Figure 61. Write Logic 1 into R/W Bit

PERFORM READ

READ 0x54

R/W BIT HIGH

DATA READ ON FALLING CLOCK EDGE

SDIO (IN)

SCLK

SDIO (OUT)

Figure 62. Perform Read

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