ADL5206ACPZ-R7 datasheet(22/25 Pages) AD

22 / 25 page

ADL5206

Data Sheet

Rev. 0 | Page 22 of 25

DIGITAL INTERFACE OVERVIEW

The three digital control interface options for the ADL5206

DGA include the following:

•

Parallel control interface

•

Serial peripheral interface

•

Gain step-up and step-down interface

The digital control interface selection is made via two digital

pins, MODE1 and MODE0, as shown in Table 9.

The same physical pins are shared between three interfaces,

resulting in as many as three different functions per digital pin

(see Table 5).

Table 9. Digital Control Interface Selection Truth Table

MODE1

MODE0

Interface

Parallel, high performance

Serial

Up and down

Parallel, low power

Parallel Digital Interface

The parallel digital interface uses five gain control bits and a

latch pin. The LATCH pin controls whether the input data latch

is transparent (logic low) or latched (logic high). In transparent

mode, the gain changes as the input gain control bits change. In

latched mode, the gain is determined by the latched gain setting

and is not changed by changing the input gain control bits.

SPI

The SPI uses three pins (SDIO, SCLK, and CS) in 3-wire SPI

mode and four pins (SDI, SDO, SCLK, and CS) in 4-wire SPI

mode. The SPI data register consists of eight bits: five gain

control bits (D0 to D4), two attenuation step size address bits

(FA0 and FA1), and one read/write bit (R/W), as shown in

Figure 58.

FA0

FA1

READ/WRITE

FAST ATTACK

GAIN CONTROL

LSB

DATA

MSB LSB MSB

R/W

Figure 58. 8-Bit SPI Register

The SPI uses a bidirectional pin (SDIO) for writing to the SPI

Whereas in 4-wire SPI mode, SDI is dedicated to writing to the

SPI register of the device, and SDO is dedicated to reading from

the SPI register of the device. To write to the SPI register, pull

the CS pin low and apply 8 clock pulses to shift the 8 bits into

the corresponding SPI register, MSB first.

The SPI register read back operation is described in the SPI

Read section.

SPI fast attack mode is controlled by the FA pin. A logic high on

the FA pin results in an attenuation selected by the FA1 and the

FA0 bits in the SPI register.

Table 10. SPI 2-Bit Attenuation Step Size Truth Table

FA1

FA0

Step Size (dB)

Up and Down Interface

The up and down interface uses two digital pins to control the

gain. When the UPDN_DAT pin is low, the gain is increased by

a clock pulse on the UPDN_CLK pin (rising and falling edges).

When the UPDN_DAT pin is high, the corresponding gain is

decreased by a clock pulse on the UPDN_CLK pin. Reset is

detected when the rising edge of UPDN_CLK latches one

polarity on UPDN_DAT, and the falling edge latches the opposite

polarity. Reset results in a minimum gain code of 11110.

UPDN_DAT

RESET

UPDN_CLK

Figure 59. Up and Down Gain Control Timing

The step size is selectable by the GS1 and GS0 pins. The default

step size is 1 dB. The gain code count rails at the top and bottom

of the control range.

Table 11. Step Size Control Truth Table

GS1

GS0

Step Size (dB)

ADL5206ACPZ-R7 Datasheet(PDF) 22 Page - Analog Devices

ADL5206ACPZ-R7 Datasheet(HTML) 22 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

Datasheet Download

Link URL