ADL5206

Data Sheet

Rev. 0 | Page 8 of 25

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

14

13

12

VOUT–

15 VOUT+

PWUP

DNC

11 LATCH/SPI_HP_LP

VCM

MODE0

MODE1

SDIO/SDO

SCLK/D4

NOTES

1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THESE PINS.

2. EXPOSED PAD GROUND. THE EXPOSED PAD MUST BE

CONNECTED TO A LOW IMPEDANCE GROUND PLANE.

ADL5206

TOP VIEW

(Not to Scale)

Figure 5. Pin Configuration (Top View)

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

VCM

Common-Mode Output.

2

MODE1

The MSB for Mode Control. Use both the MODE0 and MODE1 pins to select high performance or to

select low power parallel, SPI, or up and down interface mode.

3

MODE0

The LSB for Mode Control. Use both the MODE1 and MODE0 pins to select parallel, SPI, or UPDN mode.

4

SDIO/SDO

Serial Data Input and Output in 3-Wire SPI Mode (SDIO). Serial data output in 4-wire SPI mode (SDO).

5

SCLK/D4

Serial Clock Input/Digital Bit 4. Depending on the selection of the MODE0 and MODE1 pins, this pin

has two functions. In serial or SPI mode, this pin functions as SCLK. In parallel mode, this pin

represents D4 when in the parallel gain control interface.

6

CS/GS1/D3

Chip Select (Active Low)/Gain Step 1/Digital Bit 3. Depending on the selection of the MODE0 and

MODE1 pins, this pin has three functions. In serial or SPI mode, this pin becomes CS. When in UPDN

mode, the GS1 function is enabled for this pin, which controls the MSB gain step size. In parallel

mode, this pin represents D3 when in the parallel gain control interface.

7

FA/GS0/D2

Fast Attack/Gain Step 0/Digital Bit 2. Depending on the selection of the MODE0 and MODE1 pins,

this pin has three functions. In serial or SPI mode, the FA function of this pin is enabled. The FA

function allows the user to define a larger attenuation jump in the digital gain control settings. The

FA pin attenuates according to an FA SPI word definition of FA0 and FA1 (the attenuation step size

bits), which is defined by the user. When in UPDN mode, the GS0 function is enabled for this pin

which controls the LSB gain step size. In parallel mode, this pin represents D2 when in the parallel

gain control interface.

8

UPDN_CLK/D1/SDI

Clock Interface for Up and Down Interface (UPDN_CLK). Depending on MODE0 and MODE1 selection,

this pin has three functions. In the up and down interface mode, this pin becomes UPDN_CLK. In

parallel mode, this pin represents Digital Bit 1 (D1) when using a parallel gain control interface. In

4-wire SPI mode, this pin is the serial data input (SDI).

9

UPDN_DAT/D0/3SPI_4SPI

Data Interface for Up and Down Interface (UPDN_DAT). Depending on MODE0 and MODE1 selection,

this pin has three functions. In up and down interface mode, this pin becomes UPDN_DAT. In parallel

mode, this pin represents Digital Bit 0 (D0) when using a parallel gain control interface. In SPI mode,

logic low selects 3-wire SPI and logic high selects 4-wire SPI (3SPI_4SPI).

10, 12

DNC

Do Not Connect. Do not connect to these pins.