ADL5206ACPZ-R7 datasheet(21/25 Pages) AD

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Data Sheet

ADL5206

Rev. 0 | Page 21 of 25

APPLICATIONS INFORMATION

BASIC CONNECTIONS

Figure 57 shows the basic connections for operating the

ADL5206.

Apply a 3.3 V or 5 V voltage to the VPOS pins. Decouple the

supply pins with at least one low inductance, surface-mount, 0.1

µF ceramic capacitor and place the capacitor as close to the

device as possible.

The differential outputs (VOUT+ and VOUT−) have a dc

common-mode voltage that is approximately half of the supply.

Therefore, decouple these outputs using 0.1 µF capacitors to

balance the load. The balanced differential inputs have the same

dc common-mode voltage as the outputs. Note that the inputs

are decoupled using 0.1 µF capacitors as well. The digital pins

(that is the mode control pins, the associated SPI and parallel

gain control pins, the power mode, and the PWUP pin) operate

at a 3.3 V voltage.

To enable the ADL5206, pull the PWUP pin high (2.0 V ≤

PWUP ≤ 3.3 V).

A logic low on the PWUP pin sets the ADL5206 to sleep mode,

reducing the current consumption to approximately 7 mA. The

VCOM pin is the output common-mode voltage, and the

VCOM pin must be decoupled with a 0.1 µF capacitor for

filtering noise.

VOUT–

VOUT+

PWUP

DNC

LATCH/SPI_HP_LP

VCOM

MODE0

MODE1

SDIO/SDO

SCLK/D4

VCOM

MODE0

MODE1

SDIO/SDO

SCLK/D4

NOTES

1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THESE PINS.

2. EXPOSED PAD GROUND. THE EXPOSED PAD MUST BE

CONNECTED TO A LOW IMPEDANCE GROUND PLANE.

ADL5206

EXPOSED

PAD

BALANCED

LOAD

5PO_VCC

0.1µF

BALANCED

SOURCE

0.1µF

½RS

LATCH/SPI_HP_LP

Figure 57. Basic Connections

ADL5206ACPZ-R7 Datasheet(PDF) 21 Page - Analog Devices

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