LAN83C171 datasheet(32/90 Pages) SMSC

32 / 90 page

JUMPER OPTIONS (EEPROM/RAM)

There are several operational modes in the

LAN83C171 which are selected by "jumpers" at

power-up reset. Actual jumpers do not need to

be installed on the board. The options can be

set by external pull-up or pull-down resistors at

manufacturing time. Pins MD[4:0] are used to

make the jumper selections.

The pins are

latched shortly after nRST goes inactive.

The

jumpers are not sampled after soft reset. A pull-

down resistor sets the jumper value to 0, and a

pull-up sets it to 1. The jumpers are defined as

follows:

MD[5] AUXILIARY POWER PRESENT - When

set to 1, indicates the presence of auxiliary

power to support the monitoring of the network

for wake-up events upon the loss of PCI Bus

power.

MD[4]

EEPROM TEST - When set to 1, the

EEPROM clock is sped up for test purposes.

MD[3] BYPASS EEPROM RECALL - When set

to 1, the EEPROM recall

is not performed after

power-up reset. Used for test purposes only.

MD[2] nBIG EEPROM - Indicates the size of the

serial EEPROM.

0 = 128x16 or 256x16, 1 =

16x16 or 64x16.

MD[1:0] EXTERNAL BUFFER SIZE SELECT -

Indicates the size of the

external receive RAM

according to the following table:

MD [1]

MD [0]

BUFFER SIZE

0 Kbytes

16 Kbytes

32 Kbytes

128 Kbytes

Advanced Configuration and Power Interface

(ACPI) Support

The EPIC incorporates all of the requirements

and most of the optional features needed to

comply with the network device class and PCI

bus

class

sub-specifications

the

ACPI

specification. The provided power management

capabilities within the EPIC can be determined

by accessing the “Power Management Register

Block” located in the EPIC PCI configuration

address

space.

The

Power

Management

or query the chip power state and to enable

wake-up notification.

Wake-Up Events and Notification

The EPIC can be enabled to provide wake-up

notification upon the occurrence of a power

management event (PME). The EPIC supports

the detection of a Magic Packet and the

occurrence of a network link-down event as

PMEs. The detection of a Magic Packet can be

enabled to generate a wake-up notification by

setting the Magic Packet Enable bit in the

General

Control

Likewise,

the

occurrence of a link-down event can be enabled

to generate a wake-up notification by setting the

appropriate enable bit in the PHY’s interrupt

mask register.

The monitoring of wake-up

events will only occur when the EPIC is in one of

the low power modes.

The software driver can specify if the EPIC

notifies the OS of the occurrence of a PME via

the Power Management Control and Status

E0h Configuration Address Space).

If an

enabled PME has occurred (bit 15/PMCSR set)

and the EPIC is enabled to notify the OS (bit

8/PMCSR set), the EPIC will assert the signal

nPME.

(Note: nPME can be asserted and

deasserted asynchronously to the PCI clock).

The EPIC will deassert nPME when the driver

either clears the PME status bit (bit 15) or

disables the notification of a PME (bit 8) in the

LAN83C171 Datasheet(PDF) 32 Page - SMSC Corporation

LAN83C171 Datasheet(HTML) 32 Page - SMSC Corporation

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