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LAN83C171 Datasheet(PDF) 40 Page - SMSC Corporation

Part # LAN83C171
Description  EPIC/XF ACPI/PC 97 Compliant Integrated PCI 10/100 Mbps Fast Ethernet Controller
PDF  90 Pages
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Manufacturer  SMSC [SMSC Corporation]
Direct Link  http://www.smsc.com
Logo SMSC - SMSC Corporation

LAN83C171 Datasheet(HTML) 40 Page - SMSC Corporation

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1 - NON-DEFERRED TRANSMISSION: This
bit
is
set
if
the
frame
is
transmitted
successfully without deferring.
A deferred
transmission can only occur the first time an
attempt is made to send a packet. Collisions
are not deferred transmissions.
0 - PACKET TRANSMITTED: This bit is set to
indicate transmission
of a packet without
excessive collisions or abort.
DWORD 1 - DATA BUFFER/START OF
FRAGLIST
POINTER
bit
Number
Description
31 through 0: Starting address of data buffer
or
fragment list in host memory space.
Fragment list must be DWORD aligned. Data
buffer may be aligned on any byte.
DWORD 2 - CONTROL/DATA LENGTH Bit
Number Description
31 through 21 Reserved: Must always be set
to 0.
20 - LASTDESCR: Indicates that this is the
last descriptor for the current transmit frame
(Not used when FRAGLIST = 1).
19 - NOCRC: Disable automatic CRC generation
for this packet when set.
18 - IAF: When set, interrupt after this frame is
transmitted.
17 - LFFORM: Fragment list format - A "1"
indicates that the data length field comes before
the pointer in the fragment list. "0" indicates that
the pointer comes before the data length.
16 - FRAGLIST: Indicates that this descriptor
points to a fragment list.
15 through 0 - Length of data buffer (Not used
when FRAGLIST = 1).
DWORD 3 - NEXT DESCRIPTOR POINTER Bit
Number Description
31 through 2 - Starting address of next descriptor
in host memory space.
Descriptors must be
DWORD aligned.
1 - 0: Unused.



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