LAN83C171 datasheet(52/90 Pages) SMSC

52 / 90 page

14 - SELECT TX CLOCK F/F:

See bit 15

description.

13 through 8: Unused.

7 - ALTERNATE DIRECTION: When set, the

alternate data value is input from the MII

management data pin, if serial management

interface is disabled.

6 - ALTERNATE DATA: Reading this bit returns

the value at the MII management data pin. A

value written to this bit will be driven onto the

MII management data pin when the serial

management interface is disabled and the

alternate direction bit is set to ouput.

5 - ALTERNATE CLOCK SOURCE:

This

clock pin when the serial management interface

disabled.

When

set,

the

management

interface clock is set.

ENABLE

SERIAL

MANAGEMENT

INTERFACE:

This

bit

selects between the

serial management

interface and a general

purpose interface muxed with the management

interface clock and data pins.

When set, the

serial management interface is selected.

The

default for this bit is set (1).

3 - PHY PRESENT: This bit is read only. It is

set to one when the MDIO line is at a logic one

value indicating the presence of a PHY device.

2 - 694 LINK STATUS: This bit is read only and

returns the value of the 694LNK pin on the

LAN83C171.

1 - ENABLE 694: When set, the EN694 pin of

the LAN83C171 is driven to a logic one. When

clear, the EN694 pin is driven low.

0 - SERIAL MODE ENABLE: When set, the MII

interface functions serially as a 7-wire interface.

This

mode

should

enabled

when

the

LAN83C171 is connected to a 10Mb/s serial

PHY device.

When clear, the MII interface

operates

defined

the

IEEE

802.3

Reconciliation Sublayer and Media Independent

Interface(MII) Draft Standard.

3C - INTERPACKET GAP Register

Reset Value: 011110001100000

This register is used to program the interpacket

gap protocol timer. It contains two values. The

first 8 bit value is used to set the total

interpacket gap time used by the transmit state

machine for deferral.

The second 7-bit value

sets the first interframe spacing value used in

the deference process.

31 through 15: Unused.

14 through 8 - INTERFRAME SPACING -PART

ONE: This 7 bit value sets the first part of the

interframe spacing delay time. The default is 60

bit times.

7 through 0 - INTERPACKET GAP TIME: This

8 bit value sets the interpacket gap delay time.

The default is 96 bit times.

40 through 48 - LAN ADDRESS Registers

Reset Value (Power Up): Unknown

These registers hold the 48-bit LAN address for

the adapter.

They are recalled from the

EEPROM after (hard)reset.

31 through 16: Unused.

15 through 0 - LAN ADDRESS: The Destination

address described as:

[N1][N0][N3][N2][N5][N4][N7][N6][N9][N8][N11][N10]

Where each N is one nibble it will be mapped to

the LAN address registers as follows:

LAN0

[15-12] = N3

LAN0

[11-8] = N2

LAN0

[7-4] = N1

LAN83C171 Datasheet(PDF) 52 Page - SMSC Corporation

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