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LAN83C171 Datasheet(PDF) 72 Page - SMSC Corporation |
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LAN83C171 Datasheet(HTML) 72 Page - SMSC Corporation |
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72 / 90 page ![]() 72 TIMING DIAGRAMS FIGURE 6 - PCI COMMAND TIMING MASTER TARGET NAME MIN MAX MIN MAX DESCRIPTION t1 7ns Input setup to clock t2 2ns 11ns 0ns (Master) Clock to signal valid delay (Target) Input hold time from clock t3 2ns 11ns Clock to signal valid delay t2 t1 t3 t1 t3 t3 t2 PCI_CBE.TD PCICLK nFRAME nCBE |
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