LAN83C171 datasheet(38/90 Pages) SMSC

38 / 90 page

LAN83C171

control

functions

will

not

accessible through memory address space

while

the ROM address decode enable bit is

set.

When

the

expansion

Flash RAM

read,

the LAN83C171 always returns all four bytes in

the dword being accessed regardless of the byte

enables active. The Flash RAM can also be

written by writing to an address in the range

defined by the ROM base address register.

The data can be programmed into the flash

RAM by following the specifications supplied by

the flash manufacturer. The write pulse for each

individual byte write will be 200 ns.

The

EPIC/100 will write all bytes in a dword that

have valid byte enables during the data phase. If

an access is made to the LAN83C171 while a

flash write is physically taking place, a retry will

be issued on the PCI bus.

ROM

DECODE

ENABLE

MEMORY

MAP ENABLE

MEMORY

SPACE

ENABLE

I/O SPACE

ENABLE

EXPANSION

ROM

CONTROL

REGISTERS

Enabled

I/O Space

Enabled

Disabled

I/O Space

Disabled

I/O & Memory

Disabled

Mem. Space

Disabled

I/O Space

Disabled

I/O Space

Disabled

After reset, the ROM will be disabled and the

ROM base address will be unknown.

The

system POST code will map the ROM into host

memory space, copy its contents into system

RAM and execute the ROM initialization code (if

no ROM signature is found, the system will

disable the ROM and proceed with the next PCI

device). The ROM initialization code is allowed

to perform dynamic re-sizing of the runtime

code in order to use as little of the host memory

space as possible.

LAN83C171 Datasheet(PDF) 38 Page - SMSC Corporation

LAN83C171 Datasheet(HTML) 38 Page - SMSC Corporation

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