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LAN83C171 Datasheet(PDF) 74 Page - SMSC Corporation |
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LAN83C171 Datasheet(HTML) 74 Page - SMSC Corporation |
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74 / 90 page ![]() 74 FIGURE 8 - PCI/nIRDY AND nTRDY TIMING MASTER TARGET NAME MIN MAX MIN MAX DESCRIPTION t1 7ns Input setup time to clock t2 2ns 11ns 0ns (Master) Clock to signal valid delay (Target) Input hold time from clock t3 7ns Input setup time to clock t4 0ns 2ns 11ns (Master) Input hold time from clock (Target) Clock to signal valid delay t5 2ns 11ns Clock to signal valid delay t6 2ns 11ns Clock to signal valid delay t2 t4 t6 t5 t1 t3 PCI_IRTR.TD PCICLK nIRDY nTRDY |
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