OPA615ID datasheet(15/26 Pages) TI

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SAMPLING COMPARATOR

Offset (V) +

Charge (pC)

HTotal (pF)

OPA615

SBOS299B – FEBRUARY 2004 – REVISED JULY 2005

This innovative circuit achieves the high slew rate

representative of an open-loop design. In addition,

The OPA615 sampling comparator features a very

the acquisition slew current for a hold or storage

short switching (2.5ns) propagation delay and utilizes

capacitor is higher than standard diode bridge and

a new switching circuit architecture to achieve excel-

switch configurations, removing a main contributor to

lent speed and precision.

the limits of maximum sampling rate and input fre-

quency.

It provides high impedance inverting and noninverting

analog inputs, a high-impedance current source out-

The switching circuits in the OPA615 use current

put and a TTL-CMOS-compatible Hold Control Input.

steering (versus voltage switching) to provide im-

proved isolation between the switch and analog

The sampling comparator consists of an operational

sections. This design results in low aperture time

transconductance amplifier (OTA), a buffer amplifier,

sensitivity to the analog input signal, reduced power

and a subsequent switching circuit. This combination

supply and analog switching noise. Sample-to-hold

is subsequently referred to as the Sampling Oper-

peak switching charge injection is 40fC.

ational Transconductance Amplifier (SOTA). The

OTA and buffer amplifier are directly tied together at

The additional offset voltage or switching transient

the buffer outputs to provide the two identical

induced on a capacitor at the current source output

high-impedance

inputs

and

high

open-loop

by the switching charge can be determined by the

transconductance. Even a small differential input

following formula:

voltage multiplied with the high transconductance

results in an output current—positive or nega-

tive—depending upon the input polarity. This charac-

teristic is similar to the low or high status of a

The switching stage input is insensitive to the low

conventional comparator. The current source output

slew rate performance of the hold control command

features high output impedance, output bias current

and compatible with TTL/CMOS logic levels. With

compensation, and is optimized for charging a ca-

TTL logic high, the comparator is active, comparing

pacitor in DC restoration, nanosecond integrators,

the two input voltages and varying the output current

peak

detectors

and

S/H

circuits.

The

typical

accordingly. With TTL logic low, the comparator

comparator output current is

±5mA and the output

output is switched off, showing a very high im-

bias current is minimized to typically

±10µA in the

pedance to the hold capacitor.

sampling mode.

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