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OPA615ID Datasheet(PDF) 23 Page - Texas Instruments |
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OPA615ID Datasheet(HTML) 23 Page - Texas Instruments |
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23 / 26 page ![]() www.ti.com BOARD LAYOUT GUIDELINES INPUT AND ESD PROTECTION External Pin +V CC −V CC Internal Circuitry OPA615 SBOS299B – FEBRUARY 2004 – REVISED JULY 2005 d) Connections to other wideband devices on the board may be made with short direct traces or Achieving optimum performance with a high- fre- through onboard transmission lines. For short quency amplifier like the OPA615 requires careful connections, consider the trace and the input to the attention to printed circuit board (PCB) layout para- next device as a lumped capacitive load. Relatively sitics and external component types. Recommen- wide traces (50mils to 100mils) should be used, dations that will optimize performance include: preferably with ground and power planes opened up around them. a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic e) Socketing a high-speed part like the OPA615 is capacitance on the output and inverting input pins not recommended. The additional lead length and can cause instability; on the non-inverting input, it can pin-to-pin capacitance introduced by the socket can react with the source impedance to cause uninten- create an extremely troublesome parasitic network tional bandlimiting. To reduce unwanted capacitance, which can make it almost impossible to achieve a a window around the signal I/O pins should be smooth, stable frequency response. Best results are opened in all of the ground and power planes around obtained by soldering the OPA615 directly onto the those pins. Otherwise, ground and power planes PCB. should be unbroken elsewhere on the board. b) Minimize the distance (< 0.25") from the power supply pins to high frequency 0.1 µF decoupling The OPA615 is built using a very high-speed, comp- capacitors. At the device pins, the ground and power lementary bipolar process. The internal junction plane layout should not be in close proximity to the breakdown voltages are relatively low for these very signal I/O pins. Avoid narrow power and ground small geometry devices. These breakdowns are re- traces to minimize inductance between the pins and flected in the Absolute Maximum Ratings table where the decoupling capacitors. The power-supply connec- an absolute maximum ±6.5V supply is reported. All tions should always be decoupled with these capaci- device pins have limited ESD protection using internal tors. An optional supply-decoupling capacitor across diodes to the power supplies, as shown in Figure 53. the two power supplies (for bipolar operation) will improve 2nd-harmonic distortion performance. Larger (2.2 µF to 6.8µF) decoupling capacitors, effective at a lower frequency, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PCB. c) Careful selection and placement of external components will preserve the high frequency performance of the OPA615. Resistors should be a very low reactance type. Surface-mount resistors Figure 53. Internal ESD Protection work best and allow a tighter overall layout. Metal-film and carbon composition, axially-leaded resistors can also provide good high frequency performance. These diodes also provide moderate protection to Again, keep these leads and PCB trace length as input overdrive voltages above the supplies. The short as possible. Never use wirewound-type re- protection diodes can typically support 30mA continu- sistors in a high frequency application. Other network ous current. Where higher currents are possible (for components, such as noninverting input termination example, in systems with ±15V supply parts driving resistors, should also be placed close to the package. into the OPA615), current-limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible since high values degrade both noise performance and frequency re- sponse. 23 |
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