DP8428 datasheet(19/26 Pages) NSC

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Switching Characteristics

All A C parameters are specified with the equivalent load

capacitances including traces of 88 DRAMs organized as 4

banks of 22 DRAMs each Maximums are based on worst-

case conditions including all outputs switching simulta-

neously This in many cases results in the AC valves

shown in the DP84XX DRAM controller data sheet being

much looser than true worst case maximum AC delays The

system designer should estimate the DP8429 load in his

her application and modify the appropriate A C parame-

ters using the graph in

Figure 10 Two example calculations

are provided below

TLF8649 – 28

FIGURE 10 Change in Propagation Delay

relative to ‘‘true’’ (application) load minus

AC specified data sheet load

Examples

A mode 4 user driving 2 banks of DRAM has the follow-

ing loading conditions

CAS

- 300 pF

Q0 – Q9 - 250 pF

RAS

- 150 pF

AC parameters should be adjusted in accordance with

Fig-

ure 10 and the specifications given for the 88 DRAM load as

follows

max tRPDL e 20 ns b 0ns e 20 ns (since RAS load-

ing is the same as that which is spec’ed)

max tCPDL e 32 ns b 7ns e 25 ns

max tCCAS e 46 ns b 7ns e 39 ns

max tRCC e 41 ns b 6ns e 35 ns

min tRHA is not significantly effected since it does not

involve an output transition

Other parameters are adjusted in a similar manner

A mode 5 user driving one bank of DRAM has the

following loading conditions

CAS - 120 pF

Q0 – Q9 - 100 pF

RAS - 120 pF

A C parameters should be adjusted as follows

with RAHS e ‘‘1’’

max tRICL e 70 ns b 11 ns e 59 ns

max tRCDL e 55 ns a 1ns b 11 ns e 45 ns

(the a 1 ns is due to lighter RAS loading the b 11 ns

is due to lighter CAS loading)

min tRAH e 15 ns a 1ns e 16 ns

The additional 1 ns is due to the fact that the RAS line

is driving less (switching faster) than the load to which

the 15 ns spec applies The row address will remain

valid for about the same time irregardless of address

loading since it is considered to be not valid at the

beginning of its transition

TLF8649 – 29

FIGURE 11 Output Load Circuit

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