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DP8428 Datasheet(PDF) 21 Page - National Semiconductor (TI) |
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DP8428 Datasheet(HTML) 21 Page - National Semiconductor (TI) |
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21 / 26 page  Switching Characteristics DP8428 and DP8429 (Continued) VCC e 50V g 10% 0 C s TA s 70 C unless otherwise noted (Notes 2 4 5) the output load capacitance is typical for 4 banks of 22 DRAMs each or 88 DRAMs including trace capacitance These values are Q0-Q9 CL e 500 pF RAS0–RAS3 CL e 150 pF WE CL e 500 pF CAS CL e 600 pF RL e 500X unless otherwise noted See Figure 11 for test load Maximum propagation delays are specified with all outputs switching Preliminary Symbol Access Parameter Condition CL All CL e 50 pF Units Min Max Min Max tRCDL1 RAS to CAS Low Delay Figure 6 34 63 ns (RAHS e 1) DP8428-8029-80 tRCDL1 RAS to CAS Low Delay Figure 6 34 55 ns (RAHS e 1) DP8428-7029-70 tRCDH RAS to CAS High Delay Figure 6 22 ns tRAH0 Row Address Hold Time Figure 6 25 25 ns (RAHS e 0 Mode 5) tRAH1 Row Address Hold Time Figure 6 15 15 ns (RAHS e 1 Mode 5) tASC Column Address Set-up Time Figure 6 00 ns (Mode 5) tRCV0 RASIN to Column Address Figure 6 94 ns Valid (RAHS e 0 Mode 5) DP8428-8029-80 tRCV0 RASIN to Column Address Figure 6 85 ns Valid (RAHS e 0 Mode 5) DP8428-7029-70 tRCV1 RASIN to Column Address Figure 6 76 ns Valid (RAHS e 1 Mode 5) DP8428-8029-80 tRCV1 RASIN to Column Address Figure 6 68 ns Valid (RAHS e 1 Mode 5) DP8428-7029-70 tRPDL RASIN to RAS Low Delay Figures 5a 5b 6 21 18 ns tRPDH RASIN to RAS High Delay Figures 5a 5b 6 20 17 ns tASRL Address Set-up to RASIN low Figures 5a 5b 6 13 ns tAPD Address Input to Output Figures 5a 5b 6 36 25 ns Delay tSPD Address Strobe High to Figures 5a 5b 48 ns Address Output Valid tASA Address Set-up Time to ADS Figures 5a 5b 6 5ns tAHA Address Hold Time from ADS Figures 5a 5b 6 10 ns tADS Address Strobe Pulse Width Figures 5a 5b 6 26 ns tWPD WIN to WE Output Delay Figure 5b 28 ns tCPDL CASIN to CAS Low Delay Figure 5b 17 33 ns (RC low Mode 4) tCPDH CASIN to CAS High Delay Figure 5b 13 33 ns (RC low Mode 4) tCPdif tCPDL -tCPDH See Mode 4 13 ns Description tRCC Column Select to Column Figure 5a 41 ns Address Valid tRCR Row Select to Row Figures 5a 5b 45 ns Address Valid tRHA Row Address Held from Figure 5a 7ns Column Select tCCAS RC Low to CAS Low Delay Figure 5a 50 ns (CASIN Low Mode 4) DP8428-8029-80 tCCAS RC Low to CAS Low Delay Figure 5a 46 ns (CASIN Low Mode 4) DP8428-7029-70 tDIF1 Maximum (tRPDL -tRHA) See Mode 4 7 ns Description tDIF2 Maximum (tRCC -tCPDL)13 ns 21 |
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