DP8428 datasheet(16/26 Pages) NSC

16 / 26 page

Applications (Continued)

TLF8649 – 24

FIGURE 7c Typical Application of DP8428 Using Modes 5 and 1

The DP84XX2 family of inexpensive preprogrammed medi-

um Programmable Array Logic devices (PALs) have been

developed to provide an easy interface between various mi-

croprocessors and the DP84XX family of DRAM controller

drivers These PALs interface to all the necessary control

signals of the particular processor and the DP8429 The

PAL controls the operation of the DP8429 in modes 5 and 1

while meeting all the critical timing considerations discussed

above The refresh clock RFCK may be divided down from

the processor clock using an IC counter such as the

DM74LS393 or the DP84300 programmable refresh timer

The DP84300 can provide RFCK periods ranging from 154

s to 156 ms based on an input clock of 2 to 10 MHz

Figure 8 shows a general block diagram for a system using

the DP8429 in modes 1 and 5

Figure 9 shows possible

timing diagrams for such a system (using WAIT to prohibit

access when refreshing) Although the DP84XX2 PALs are

offered as standard peripheral devices for the DP84XX

DRAM controllerdrivers the programming equations for

these devices are provided so the user may make minor

modifications for unique system requirements

ADVANTAGES OF DP8429 OVER

A DISCRETE DYNAMIC RAM CONTROLLER

1) The DP8429 system solution takes up much less board

space because everything is on one chip (latches re-

fresh counter control logic multiplexers drivers and in-

ternal delay lines)

2) Less effort is needed to design a memory system The

DP8429 has automatic modes (1 and 5) which require a

minimum of external control logic Also programmable ar-

ray logic devices (PALs) have been designed which allow

an easy interface to most popular microprocessors (Mo-

torola 68000 family National Semiconductor 32032 fami-

ly Intel 8086 family and the Zilog Z8000 family)

3) Less skew in memory timing parameters because all crit-

ical components are on one chip (many discrete drivers

specify a minimum on-chip skew under worst-case condi-

tions but this cannot be used if more then one driver is

needed such as would be the case in driving a large

dynamic RAM array)

4) Our switching characteristics give the designer the critical

timing specifications based on TTL output levels (low e

08V high e 24V) at a specified load capacitance All

timing parameters are specified on the DP8429

A) driving 88 DRAM’s over a temperature range of 0 – 70

degrees centigrade (no extra drivers are needed)

B) under worst-case driving conditions with all outputs

switching simultaneously (most discrete drivers on the

market specify worst-case conditions with only one

output switching at a time this is not a true worst-case

condition)

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