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DP8428 Datasheet(PDF) 22 Page - National Semiconductor (TI) |
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DP8428 Datasheet(HTML) 22 Page - National Semiconductor (TI) |
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22 / 26 page  Switching Characteristics DP8428 and DP8429 (Continued) VCC e 50V g 10% 0 C s TA s 70 C unless otherwise noted (Notes 2 4 5) The output load capacitance is typical for 4 banks of 22 DRAMs each or 88 DRAMs including trace capacitance These values are Q0-Q9 CL e 500 pF RAS0–RAS3 CL e 150 pF WE CL e 500 pF CAS CL e 600 pF RL e 500X unless otherwise noted See Figure 11 for test load Maximum propagation delays are specified with all outputs switching Preliminary Symbol Refresh Parameter Condition CL All CL e 50 pF Units Min Max Min Max tRC Refresh Cycle Period Figure 2a 100 ns tRASINLH Pulse Width of RASIN Figure 2a 50 ns during Refresh tRFPDL0 RASIN to RAS Low Delay Figure 2a 28 ns during Refresh (Mode 0) tRFPDL5 RASIN to RAS Low Delay Figure 7 38 ns during Hidden Refresh tRFPDH0 RASIN to RAS High Delay Figure 2a 35 ns during Refresh (Mode 0) tRFPDH5 RASIN to RAS High Delay Figure 7 44 ns during Hidden Refresh tRFLCT RFSH Low to Counter Figures 2a 3 38 ns Address Valid CS e X tRFLRL RFSH Low Set-up to RASIN Figure 2a 12 ns Low (Mode 0) to get Minimum tASR e 0 tRFHRL RFSH High Setup to Access Figure 3 25 ns RASIN Low tRFHRV RFSH High to Row Figure 3 43 ns Address Valid tROHNC RAS High to New Count Figure 2a 42 ns Valid tRST Counter Reset Pulse Width Figure 2a 60 ns tCTL RFIO Low to Counter Figure 2a 100 ns Outputs All Low tRFCKLH Minimum Pulse Width Figure 7 100 ns of RFCK T Period of RAS Generator Figure 3 30 ns Clock tRGCKL Minimum Pulse Width Low Figure 3 15 ns of RGCK tRGCKH Minimum Pulse Width High Figure 3 15 ns of RGCK tFRQL RFCK Low to Forced RFRQ Figure 3 66 ns (RFIO) Low CL e 50 pF RL e 35k tFRQH RGCK Low to Forced RFRQ Figure 3 55 ns High CL e 50 pF RL e 35k 22 |
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