DP8428 datasheet(14/26 Pages) NSC

14 / 26 page

DP8428DP8429 Mode Descriptions (Continued)

Once it is started a hidden refresh will continue even if

RFCK goes low However CS must be high throughout the

refresh (until RASIN goes high)

These hidden refreshes are valuable in that they do not

delay accesses When determining the duty cycle of RFCK

the high time should be maximized in order to maximize the

probability of hidden refreshes If a hidden refresh doesn’t

happen then a refresh request will occur on RFIO when

RFCK goes low After receiving the request the system

must perform a refresh while RFCK is low This may be

done by going to mode 1 and allowing an automatic refresh

(see mode 1 description) This refresh must be completed

while RFCK is low thus the RFCK low time is determined by

the worst-case time required by the system to respond to a

refresh request

(External Refresh)

This refresh scheme is identical to that in (b) except that

after receiving a refresh request mode 0 is entered to do

the refresh (see mode 0 description) The refresh request is

terminated (RFIO goes high) as soon as mode 0 is en-

tered This method requires more control than using mode 1

(auto-refresh) however it may be desirable if the mode 1

refresh time is considered to be excessive

Example

Figure 7b demonstrates how a system designer would use

the DP8429 in mode 5 based on certain characteristics of

his system

System Characteristics

1) DRAM used has min tRAH requirement of 15 ns and

min tASR of0ns

2) DRAM address is valid from time TV to the end of the

memory cycle

3) four banks of twenty-two 256k memory chips each are

being driven

Using the DP8429 (see

Figure 7b )

1) Tie pin 4 (RAHS) high to guarantee a 15 ns minimum

tRAH which is sufficient for the DRAMs being used

2) Generate RASIN no earlier than time TV a tASRL (see

switching characteristics) so that the row address is

valid on the DRAM address inputs before RAS occurs

3) Tie ADS high since latching the DRAM address on the

DP8429 is not necessary

4) Connect the first 20 system address bits to R0-R9 and

C0-C9 and bits 21 and 22 to B0 and B1

5) Connect each RAS output of the DP8429 to the RAS

inputs of the DRAMs of one bank of the memory array

connect Q0-Q9 of the DP8429 to A0-A9 of all DRAMs

connect CAS of the DP8429 to CAS of all the DRAMs

Figure 7c illustrates a similar example using the DP8428 to

drive two 32-bit banks

TLF8649 – 22

FIGURE 7a Hidden Refreshing (Mode 5) and Forced Refreshing (Mode 1) Timing

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