DP8428 datasheet(5/26 Pages) NSC

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DP8428 vs DP8429

The DP8428 DYNAMIC RAM CONTROLLERDRIVER is

identical to the DP8429 with the exception of two functional

differences incorporated to improve performance with 32-bit

microprocessors

1) Pin 28 (B1) is used to enabledisable a pair of RAS out-

puts and pin 29 (B0 on the DP8429) is a no connect

When B1 is low RAS0 and RAS1 are enabled such that

they both go low during an access When B1 is high

RAS2 and RAS3 are enabled This feature is useful when

driving words of 32 bits or more since each RAS would

be driving only one half of the word By distributing the

load on each RAS line in this way the DP8428 will meet

the same AC specifications driving 2 banks of 32 DRAMs

each as the DP8429 does driving 4 banks of 16 bits each

2) The hidden refresh function available on the DP8429 has

been disabled on the DP8428 in order to reduce the

amount of setup time necessary from CS going low to

RASIN going low during an access of DRAM This param-

eter called tCSRL1 is 5 ns for the DP8428 whereas it is

34 ns for the DP8429 The hidden refresh function al-

lowed only a very small increase in system performance

at microprocessor frequencies of 10 MHz and above

Pin Definitions

VCC GND GND b VCC e 5V g10% The three supply

pins have been assigned to the center of the package to

reduce voltage drops both DC and AC There are two

ground pins to reduce the low level noise The second

ground pin is located two pins from VCC so that decoupling

capacitors can be inserted directly next to these pins It is

important to adequately decouple this device due to the

high switching currents that will occur when all 10 address

bits change in the same direction simultaneously A recom-

mended solution would be a 1 mF multilayer ceramic capaci-

tor in parallel with a low-voltage tantalum capacitor both

connected as close as possible to GND and VCC to reduce

lead inductance See Figure below

TLF8649 – 8

Capacitor values should be chosen depending on the particular application

R0 – R9 Row Address Inputs

C0 – C9 Column Address Inputs

Q0 – Q9 Multiplexed Address Outputs –

This address is

selected from the Row Address Input Latch the Column

Address Input Latch or the Refresh Counter

RASIN Row Address Strobe Input –

RASIN directly con-

trols the selected RAS output when in an access mode and

all RAS outputs during hidden or external refresh

RC (RFCK) –

In the auto-modes this pin is the external

refresh clock input one refresh cycle should be performed

each clock period In the external access mode it is Row

Column Select Input which enables either the row or column

address input latch onto the output bus

CASIN (RGCK) –

In the auto-modes this pin is the RAS

Generator Clock input In external access mode it is the

Column Address Strobe input which controls CAS directly

once columns are enabled on the address outputs

ADS Address (Latch) Strobe Input –

Row Address Col-

umn Address and Bank Select Latches are fall-through with

ADS high latching occurs on high-to-low transition of ADS

CS Chip Select Input –

When high CS disables all ac-

cesses Refreshing however in both modes 0 and 1 is not

affected by this pin

M0 M2 (RFSH) Mode Control Inputs –

These pins select

one of the four available operational modes of the DP8429

(see Table III)

RFI0 Refresh InputOutput –

In the auto-modes this pin

is the Refresh Request Output It goes low following RFCK

indicating that no hidden refresh was performed while RFCK

was high When this pin is set low by an external gate the

on-chip refresh counter is reset to all zeroes

WIN Write Enable Input

WE Write Enable Output –

WE follows WIN unconditionally

RAHS Row Address Hold Time Select –

Selects the

tRAH to be guaranteed by the DP8428 or DP8429 delay line

to allow for the use of fast or slow DRAMs

CAS Column Address Strobe Output –

In mode 5 and in

mode 4 with CASIN low before RC goes low CAS goes

low automatically after the column address is valid on the

address outputs In mode 4 CAS follows CASIN directly af-

ter RC goes low allowing for nibble accessing CAS is al-

ways high during refresh

RAS 0 – 3 Row Address Strobe Outputs –

The enabled

RAS output (see Table II) follows RASIN directly during an

access During refresh all RAS outputs are enabled

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