DP8428 datasheet(13/26 Pages) NSC

13 / 26 page

DP8428DP8429 Mode Descriptions (Continued)

Indicates Dynamic RAM Parameters

TLF8649 – 20

FIGURE 6 Mode 5 Timing

(Refer to

Figure 6 ) In mode 5 the selected RAS follows

RASIN immediately as in mode 4 to strobe the row address

into the DRAMs The row address remains valid on the

DP8429 address outputs long enough to meet the tRAH re-

quirement of the DRAMs (pin 4 RAHS of the DP8429 al-

lows the user two choices of tRAH) Next the column ad-

dress replaces the row address on the address outputs and

CAS goes low to strobe the columns into the DRAMs WIN

determines whether a read write or read-modify-write is

done

The diagram below illustrates mode 5 automatic control sig-

nal generation

TLF8649 – 21

REFRESHING IN CONJUNCTION WITH MODE 5

When using mode 5 to perform memory accesses refresh-

ing may be accomplished

(a)

externally (in mode 0 or mode 1)

(b)

by a combination of mode 5 (hidden refresh) and

mode 1 (auto-refresh)

(c)

by a combination of mode 5 and mode 0

(a) Externally Controlled Refreshing in Mode 0 or Mode 1

All refreshing may be accomplished using external refresh-

es in either mode 0 or mode 1 with RC (RFCK) tied high

(see mode 0 and mode 1 descriptions) If this is desired the

system determines when a refresh will be performed puts

the DP8429 in the appropriate mode and controls the RAS

signals directly with RASIN The on-chip refresh counter is

enabled to the address outputs of the DP8429 when the

refresh mode is entered and increments when RASIN goes

high at the completion of the refresh

(b) Mode 5 Refreshing (hidden) with Mode 1 refreshing

(auto)

(Refer to

Figure 7a ) If RFCK is tied to a clock (see mode 1

description) RFIO becomes a refresh request output and

goes low following RFCK going low if no refresh occurred

while RFCK was high Refreshes may be performed in

mode 5 when the DP8429 is not selected for access (CS is

high) and RFCK is high If these conditions exist the refresh

counter contents appear on the DP8429 address outputs

and all RAS lines follow RASIN so that if RASIN goes low

(an access other than through the DP8429 occurs) all RAS

lines go low to perform the refresh The DP8429 allows only

one refresh of this type for each period of RFCK since

RFCK should be fast enough such that one refresh per peri-

od is sufficient to meet the DRAM refresh requirement

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