DP8428 datasheet(15/26 Pages) NSC

15 / 26 page

DP8428DP8429 Mode Descriptions (Continued)

TLF8649 – 23

FIGURE 7b Typical Application of DP8429 Using Modes 5 and 1

Applications

If one desires a memory interface containing the DP8429

that minimizes the number of external components required

modes 5 and 1 should be used These two modes provide

1) Automatic access to memory (in mode 5 only one signal

RASIN is required in order to access memory)

2) Hidden refresh capability (refreshes are performed auto-

matically while in mode 5 when non-local accesses are

taking place as determined by CS)

3) Refresh request capability (if no hidden refresh took

place while RFCK was high a refresh request is generat-

ed at the RFIO pin when RFCK goes high)

4) Automatic forced refresh (If a refresh request is generat-

ed while in mode 5 as described above external logic

should switch the DP8429 into mode 1 to do an automat-

ic forced refresh No other external control signals need

be issued WAIT states can be inserted into the proces-

sor machine cycles if the system tries to access memory

while the DP8429 is in mode 1 doing a forced refresh)

Some items to be considered when integrating the DP8429

into a system design are

1) The system designer should ensure that a DRAM access

not be in progress when a refresh mode is entered Simi-

larly one should not attempt to start an access while a

refresh is in progress The parameter tRFHRL specifies

the minimum time from RFSH high to RASIN going low to

initiate an access

2) One should always guarantee that the DP8429 is enabled

for access prior to initiating the access (see tCSRL1)

3) One should bring RASIN low even during non-local ac-

cess cycles when in mode 5 in order to maximize the

chance of a hidden refresh occurring

4) At lower frequencies (under 10 Mhz) it becomes increas-

ingly important to differentiate between READ and

WRITE cycles RASIN generation during READ cycles

can take place as soon as one knows that a processor

READ access cycle has started WRITE cycles on the

other hand cannot start until one knows that the data to

be written at the DRAM inputs will be valid a setup time

before CAS (column address strobe) goes true at the

DRAM inputs Therefore in general READ cycles can be

initiated earlier than WRITE cycles

5) Many times it is possible to only add WAIT states during

READ cycles and have no WAIT states during WRITE

cycles This is because it generally takes less time to

write data into memory than to read data from memory

DP8428 Datasheet(PDF) 15 Page - National Semiconductor (TI)

DP8428 Datasheet(HTML) 15 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Datasheet Download

Link URL