PCM16C02 datasheet(10/42 Pages) NSC

10 / 42 page

50 Functional Description (Continued)

Memls8

This bit is set to one (1) if common memory is

organized for 8-bit access This bit is set to zero (0) if com-

mon memory is organized for 16-bit access The default val-

ue is zero (0) This information allows the PCM16C02 to

properly access memory using the MEMWEH

and

MEMWEL

signals

CWAIT1 CWAIT0

When this bit is set to one (1) the

PCM16C02 interprets this input signal active when it is low

(0) When this bit is set to zero (0) the PCM16C02 interprets

this input signal as active when it is high (1) The default bit

value is zero (0) ie the CWAIT( ) input signal is asserted

high (1)

PMGR and Clock Register

0x03E6

The Power Manager (PMGR) and Clock Register is used for

controlling the PCNTL(10) and FCLK(10) pins for power

management purposes

Hardware power management is enabled using the Func-

tion Configuration Option Register’s PMGMT

EN(D3) bit

Its use is intended for functions that can be sequenced on

off or into idle or sleep states with a quick (k 10 ms) re-

sponse time when powered on again That is the function

may use its CWAIT( ) signal to extend a transaction that

caused the PCM16C02 to turn it on Use of the READY( )

signal in a dynamic hardware power managed environment

to set the RRdyBsy bits in order to achieve l 10 ms re-

sponse times for power on is not guaranteed to work since

system software may not inspect the RRdyBsy bit in all

such instances

F1CLKEN DIV1 PPOL1 PCNTL(1) F0CLKEN DIV0 PPOL0 PCNTL(0)

F1CLKEN

F0CLKEN

If set

these enable the pins

FCLK(10) to receive a clock out If clear the respective

pins FCLK(10) will be forced low These are set and

cleared by software if desired or statically loaded upon card

power up from the EEPROM

DIV1

DIV0

If set

the respective clock output from

FCLK(10) will be divided by 32 from the input clocks

MCLK(10) If clear the clock output FCLK(10) will equal

the respective clock input MCLK(10) These are set and

cleared by software if desired or statically loaded upon card

power up from the EEPROM

PPOL1 PPOL0

Sets the active polarity of the PCNTL(1)

and PCNTL(0) signals such that the function is asserted If

PPOL is set to zero (0) PCNTL( ) is asserted when in the

high state If set to one (1) PCNTL( ) is asserted when in

the low state The default is set to zero (0) ie PCNTL( )

defaults to active high

PCNTL(1)

PCNTL(0)

These

bits

control

the

pins

PCNTL(1) and PCNTL(0) respectively If hardware power

management is not selected in the Function Configuration

Option Register’s Function Configuration Index then these

bits may be used as output signals by software for general

purposes If the hardware power management configuration

is selected these bits are de-asserted (defined by PPOL1

0) when the PCM16C02’s CTERM 1 or 0 counter expires

These bits will be asserted if a transaction occurs to the

function through an IO window or the function requests

service by issuing a RI

IN( ) In either strategy software

may always write and read back these bits These bits de-

fault to zero (0) during power-on until the PMGR and Clock

CTERM Registers 0 1

0x03E8 0x03EA

These registers are used to define the value of function 0’s

and function 1’s power time-out counters respectively If a

function’s power time-out counter expires the PCNTL bit for

that function in the PMGR and Clock Register is de-assert-

ed This will occur if a function is in-active long enough for

it’s power time-out counter to expire Active is defined as

having either an IO access from the host or receiving a

IN( )

Devices that may operate for long periods of

time without a host IO access should follow a software

controlled power management strategy that uses the PwrDn

bits in the Function Configuration Status Registers 0 1

D7–D0

N e Time-Out Counter Terminal Count Value

Each function’s terminal counter is 8 bits wide and counts at

a rate of MCLK(0)(217) For example if the MCLK(0) fre-

quency is 30 MHz the device can be programmed to time-

out between 00s to 1114s The general formula is

Time e (1mclk(0))

217

where N e 0 1 2

255

For a 5 MHz MCLK(0) frequency the equation is

Time e N (262144 ms) where N e 012

255

Note

A value of zero implies the function is powered down

Miscellaneous Register

0x03F0

D4–D0

FastEE

RFU

EEPROMStartAddr

FastEE

If this bit is set to one (1) then the clock used to

access the EEPROM shall be MCLK(0)2 If this bit is set to

zero (0) the clock used to access the EEPROM shall be

MCLK(0)32

EEPROMStartAddr

This field contains a starting address

for EEPROM read or write access This is ordinarily set to

zero and is used for debugtest purposes

Wait State Timer Register

0x03F6

This register allows the insertion of default wait states from

the PCM16C02 using HWAIT

It is intended to be used in

situations where either the function is too slow to respond

with a CWAIT( ) or the unique wait timing constraints be-

tween the system and PC Card design necessitate a default

wait state

D7–D4

D3–D2

D1–D0

Reserved

Func1Wait

Func0Wait

Func1Wait Func0Wait

This value is the number (0 1 2

or 3) of MCLK(0) time periods that the PCM16C02 will as-

sert HWAIT

during a valid access to a particular function

For Zero wait states program these values to 00b

NAND Flash (NM29N16) Configuration Register 0x03F8

D7–D4

Reserved

mem

space

NAND

IOCS16

NAND

mem

space

Mem

space

selects

whether

NAND ReadWrite strobes are generated by accesses to

common memory space or IO space When Function 0 is

configured for NAND Flash (NM29N16) Mode if mem

space is set to 0 NAND (NM29N16) ReadWrite strobes

are generated by an IO access to the function 0 base ad-

dress a 4 If mem

space is set to 1 ReadWrite

strobes are generated by any readwrite access to common

memory

PCM16C02 Datasheet(PDF) 10 Page - National Semiconductor (TI)

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