PCM16C02 datasheet(11/42 Pages) NSC

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50 Functional Description (Continued)

NAND

IOCS16

When Function 0 is configured for NAND

Flash (NM29N16) Mode D2 replaces the external pin

IOCS16(0)

to allow the host to know if the NAND

(NM29N16) is organized for 8- or 16-bit accesses If Func-

tion 0 is NOT configured for NAND Flash (NM29N16) Mode

the bit performs no function This register gets downloaded

during EEPROM reads

If set to zero (0) PCM16C02 will assert only one of the

four external CE

pins at a time (based on the value of bits

D0 and D1 in the Device Select Register) allowing up to

four unique enable control lines

If set to one (1)

PCM16C02 will place on the external CE

lines the exact

binary number placed in bits D0 – D3 of the Device Select

15 unique CE

control lines which can control up to 30

pairs of NAND Flash (NM29N16) devices (Reference table

in Section 544 for details)

NAND

This bit if set to one (1) configures function 0

as a NAND Flash (NM29N16) interface (see Section 544

for specific function details) If set to zero (0) function 0

assumes normal IO interface functionality

Watchdog Time-Out Register

0x03FC

D5–D0

RFU

Wait

Tout Enable

RFU

Wait

Tout Enable

When this bit is set to a one (1) the

HWAIT

time-out watchdog timer is enabled In addition

the ability to set

Intr in the Function Configuration Option

Intr in the Card Configuration Register and

IREQ

is enabled once the watchdog timer expires The

watchdog timer may expire if HWAIT

is asserted for more

than approximately 112 ms when MCLK(0) is set to 20 MHz

This prevents the system from hanging due to prolonged

HWAIT

assertions If this bit is reset to zero (0) Wait

Tout and its associated interrupt capability is disabled during

HWAIT assertions

ID Register

0x1000

This read only register provides the software with IC revision

information

D7–D3

D2–D0

PCM16C02 Code e 00010b

Revision Code e 000b

NSC PCM16C02 Code

This code will may be used to

identify the NSC PCM16C02 IC The value of bits D7 – D3 of

this register is 00010 which when appended to the three

bits of the revision code produce 00010 xxx which is 1x

hex

Revision Code

This will uniquely identify the silicon ver-

sion of the PCM16C02 IC as 000b

EEPROM Access

In order to avoid accidental EEPROM overwrite

the

PCM16C02 utilizes two registers that must be written with

the proper byte sequence in order to enable EEPROM

writes In order to initiate an EEPROM write the following

Attribute Register Address Hex Data

EE Control Reg

1002

EE Security Reg

1004

EE Control Reg

1002

Failure to initiate the exact sequence will disable writes

regardless of the value placed in the WriteEEPROM or

EEPROMWriteEn bits of the EEPROM Control Register

EEPROM Control Register

0x1002

This register (in conjunction with the EEPROM Security

EEPROM as well as the EEPROM enable

D5–D1

WriteEEPROM

ReadEEPROM

Reserved

EEPROMWriteEn

WriteEEPROM

When set this tells the EEPROM control-

ler to copy the contents of the PCM16C02 Shadow RAM to

the EEPROM provided the proper write security sequence

listed above has been executed Once the EEPROM write

has completed the EEPROM controller clears this bit

ReadEEPROM

When set this tells the EEPROM control-

ler to copy the contents of the EEPROM to the shadow

RAM Once done the EEPROM controller clears this bit

Any data modified in the Shadow RAM that has not first

been written back to the EEPROM will be lost

The

EEPROM may be read independent of the value in the

EEPROMWriteEnable bit

EEPROMWriteEn

This must be set to allow EEPROM

writes If clear the EEPROM may not be written The default

value at reset is low The EEPROM may be read indepen-

dent of the value of this bit

Note 1

Upon power-up the PCM16C02 EEPROM controller copies the en-

tire contents of the lower 1 kbytes of the EEPROM into the Shadow

RAM independent of writing to the EEPROM Control Register

Note 2

The PCM16C02 EEPROM controller stores data in a 16-bit orga-

nized EEPROM in lowhigh format Although Attribute Memory is

on even byte boundaries only the entire EEPROM’s address space

is used This eliminates waste of EEPROM memory Therefore the

Attribute space used by the Shadow RAM is double the actual size

of the EEPROM For example if a 16-bit EEPROM is pre-pro-

grammed the low byte at word 0 in the EEPROM will be shadowed

at Attribute location 0x0000 and the high byte will be shadowed at

Attribute location 0x0002 The low byte at EEPROM word 1 will be

shadowed to Attribute location 0x0004 etc

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