PCM16C02 datasheet(16/42 Pages) NSC

16 / 42 page

50 Functional Description (Continued)

Device Select Register

IO window base address a 2

Bits D0 – D3 of the Device Select Register are used to assert

specific CE

pins per the function table listed below

D7–D4D3D2D1D0

RFU

NAND (NM29N16) ReadWrite Enable STROBE

IO window base address a 4

OR Any Common Memory Access

The REWE Enable Strobe allows RE

and WE

asser-

tions to be generated whenever the following conditions are

present

MEMORY SPACE ACCESS

If NAND Flash (NM29N16) Configuration Register (03F8)

bit D0 (NAND

EN) is set High and bit D3 (mem

space) is set High

(HOE

L) and (REG

(HWE

L) and (REG

IO SPACE ACCESS

If NAND Flash (NM29N16) Configuration Register (03F8)

bit D0 (NAND

EN) is set High and bit D3 (mem

space) is set Low

(Func 0 base addr a 4) and (REG

and (HIORD

(Func 0 base addr a 4) and (REG

and (HIOWR

TLF11688 – 6

TABLE 5-2 Functional Description of NAND Flash (NM29N16) Mode Register Set

Note

If BC e 0 only one CE

NAND( )

is enabled at a

time

NAND( ) ’s reflect the binary

representation of the selected

NAND (NM29N16) (up to 15)

that may be externally decod-

ed (See example below)

TLF11688 – 5

PCM16C02 Datasheet(PDF) 16 Page - National Semiconductor (TI)

PCM16C02 Datasheet(HTML) 16 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

Datasheet Download

Link URL