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VT8601 Datasheet(PDF) 124 Page - List of Unclassifed Manufacturers

Part # VT8601
Description  Single-Chip Slot-1 / Socket-370 PCI North Bridge With Integrated AGP 2D / 3D Graphics Accelerator and Advanced Memory Controller
PDF  144 Pages
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Manufacturer  ETC1 [List of Unclassifed Manufacturers]
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VT8601 Datasheet(HTML) 124 Page - List of Unclassifed Manufacturers

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VT8601 Apollo ProMedia
Revision 1.3 September 8, 1999
-118
3D Graphics Engine Registers
7HFKQRORJLHV ,QF
:H&
:H&RRQQHFW
QQHFW
GEbase + 3C –Setup Engine Primitive Type ................. WO
Writing to this register signals the Graphics Engine to begin
sequential loading. The engine will interpret the contents of
this register and the Primitive Attribute register to decide the
amount and types of parameters to expect. Like vertices, there
is a FIFO for Triangle Attributes. The queue has three entries.
Writing to this register adds it to the queue. The Setup Engine
starts working whenever a triangle attribute is received and
stops after it is finished processing a triangle with L = 1.
31-30 Loading Target
00 Rasterization Engine.
Send bits 19-0 to the
RE. Sequential loading data will also be sent
to the RE.................................................default
01 Setup Engine.
Send bits 29-0 to the SE.
Sequential loading data will also be sent to the
SE. Internally, a flag is set to prevent the SE
from decoding the data and sending it to the
RE. The SE will clear this flag when it is idle.
1x -reserved-
29
Null Primitive
0
Regular Primitive ...................................default
1
Null Primitive
28
Last Primitive
0
Regular Primitive ...................................default
1
Last Primitive
27-26 Culling Attribute (Setup Engine Target Only)
00 No culling...............................................default
01 Clockwise culling
10 Counter-clockwise culling
11 No culling
25
Reserved
........................................ always reads 0
24
(V2, V0) Edge Anti-Aliasing Flag ........... default = 0
23
(V1, V2) Edge Anti-Aliasing Flag .......... default = 0
22
(V1, V1) Edge Anti-Aliasing Flag .......... default = 0
21
Full Vertices Information
0
Partial Vertices Information.
Two of the
vertices are from the previous triangle. Only
one vertex is to be loaded from the vertex
queue to the working registers................default
1
All vertices are new.
All three working
registers are to be loaded from the vertex
queue.
20-19 Working Vertex Index
Index of the working vertex that is to be replaced.
This field is always 0 if F = 1.
18-3 Reserved
........................................ always reads 0
2
Debug Control
0
Discard triangle on overflow ..................default
1
Draw triangle on overflow
1-0
Flat Color Vertex Index
Vertex index for flat color (Index of vertex whose
color is passed to the RE as the starting color)
Vertex Registers
Inside the setup engine, one set of registers is provided to
store the three vertices is is currently working on and an
additional set is provided to store three pending vertices. Note
that it doesn’t always require 3 vertices to define a triangle
(depending on the Triangle Attribute Register, it may be either
1 or 3 vertices).
Vertex information includes coordinate, texture, color, and
depth. Some may be absent in a data stream. If any appear in
a vertex, they must be present in the following order: Color,
Specular Color, W, U, V, Z, X, Y. The formats are shown
below:
Vertex Register 1 - Color Value
31-24 Alpha Value
23-16 Red Value
15-8 Green Value
7-0
Blue Value
Vertex Register 2 - Specular Color Value
31-24 Fog Value
23-16 Specular Red Value
15-8 Specular Green Value
7-0
Specular Blue Value
Vertex Register 3 - W Value
31-0 Texture W Coordinate. 32-bit floating # in (0, 1.0)
Vertex Register 4 - U Value
31-0 Texture U Coordinate. 32-bit floating number
Vertex Register 5 - V Value
31-0 Texture V Coordinate. 32-bit floating number
Vertex Register 6 - Z Value
31-0 Z Coordinate. 32-bit floating number
Vertex Register 7 - X Value
31-0 X Coordinate. 32-bit floating number
Vertex Register 8 - Y Value
31-0 Y Coordinate. 32-bit floating number
Floating Point Number Format
All floating point numbers are converted by on-chip hardware
into internal fixed point integer format.
All floating point
numbers are specified in IEEE 32-bit floating point number
format (shown below):
31
Sign
30-23 Exponent (excess-127 format)
22-0 Mantissa (fractional part of a number in “1.nn”
format where the integer part is always 1)



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