WM8200

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PP Rev 1.22 March 2002

5

ELECTRICAL CHARACTERISTICS

Test Conditions:

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DC Accuracy

Integral nonlinearity

INL

±1.0

LSB

Differential nonlinearity

DNL

±0.3

LSB

Offset error

0.7

% of FSR

Full scale error

2.2

% of FSR

Missing codes

No missing codes guaranteed

Analogue Input Signal to AIN pins

Differential analogue input

voltage (AINP-AINN)

PGA=1x gain

-1

1

V

Switched input capacitance

1.2

pF

Conversion Characteristics

Conversion frequency

5

40

MHz

Pipeline delay

4

cycles of

CLK

Dynamic Performance (differential input mode)

9.6

Effective number of bits

ENOB

9.5

bits

72

Spurious free dynamic range

SFDR

70

dB

-72.5

Total harmonic distortion

THD

-71.6

dB

60

Signal to noise ratio

SNR

57

dB

59.7

Signal to noise and distortion

ratio

SINAD

59.6

dB

PGA

Gain range (linear scale)

0.5

4

V/V

Gain step size (linear scale)

0.5

V/V

Clamp

Clamp DAC resolution

10

bits

Clamp DAC output voltage

REFB

REFT

V

Clamp DAC DNL

±1

LSB

Clamp output voltage error

-40

40

mV

REFB, REFT internal ADC reference voltage outputs (MODE= AVDD)

VREF = 0.5V

1.75

Reference voltage top, REFT

(AVDD=3V)

VREF= 1.0V

2

VREF = 0.5V

1.25

Reference voltage bottom,

REFB (AVDD=3V)

VREF= 1.0V

1

VREF Input / Output specifications (ADC Input Range = VREFx2)

Internal 0.5V reference to VREF

REFSENSE = VREF

0.5

V

Internal 1V reference to VREF

REFSENSE = AGND

1

V

External reference applied to

VREF pin

REFSENSE = AVDD

0.5

1

V

Input impedance in internal ADC

reference mode

REFSENSE = AVDD,

MODE = AVDD

14

k

Ω