WM8200

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PP Rev 1.22 March 2002

6

Test Conditions:

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Power Supplies

MODE = AGND

28.5

mA

Analogue supply current

MODE = AVDD

31

mA

Digital supply current

5

mA

Standby power consumption

(digital and analogue combined)

75

uW

Digital Logic Levels (CMOS Levels)

Input LOW level

(Note 1)

0.2 x VDD

V

Input HIGH level

(Note 1)

0.8 x VDD

V

Output LOW

µA

0.4

V

Output HIGH

µA

VDD – 0.4

V

Notes

1.

Digital input and output levels refer to the supply used for the input/output buffer on the relevant pin. CLK and MODE

refer to the AVDD supply, all other digital input/output refers to the DVDD supply.

CONTROL INTERFACE TIMING

CSB

SCLK

SDIN

t

CSL

t

DHO

t

DSU

t

CSH

t

SCY

t

SCH

t

SCL

t

SCS

LSB

t

CSS

Figure 1: Control Interface Timing

Test Conditions

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Program Register Input Information

SCLK rising edge to CSB rising

edge

60

ns

SCLK pulse cycle time

80

ns

SCLK pulse width low

30

ns

SCLK pulse width high

30

ns

SDIN to SCLK set-up time

20

ns

SCLK to SDIN hold time

20

ns

CSB pulse width low

20

ns

CSB pulse width high

20

ns

CSB rising to SCLK rising

20

ns

Table 1 Control Interface Timing Information