WM8200

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PP Rev 1.22 March 2002

8

()

()

()

()

Gain

REFB

REFT

]

AINN

AINP

[

Gain

REFT

REFB

×

−

≤

−

≤

×

−

2

2

PROGRAMMABLE-GAIN AMPLIFIER

()

INN

INP

P

Q

V

V

Gain

V

Gain

V

−

×

=

×

=

The PGA gain defaults to 1.0 at power-up, but can be programmed from 0.5 to 4.0 in steps of 0.5.

ANALOGUE-TO-DIGITAL CONVERTER

2

REFB

REFT

−

=













−

−

=

2

REFB

REFT

V

QZS

SIGNAL CHAIN SUMMARY

Combining the above equations to find the input voltages [AINP – AINN] that correspond to the limits

of the ADCs valid input range gives:

Therefore the input signal span is given by:

Gain

REFB

REFT

AINN

AINP

−

=

−

In order to match the ADC input range to the input signal amplitude, REFT and REFB should be set

such that:

Gain

)

AINN

AINP

(

REFB

REFT

×

−

=

−

ADC REFERENCE MODES

The WM8200 references REFT and REFB can be driven from external (off-chip) sources or from the

internal reference generation/buffer circuit. The mode of operation is selected by the voltage applied

to the MODE pin. These are summarised and explained in Table 2.

Note that the internally generated ADC references are intended solely for WM8200 internal use and

REFT and REFB must not be used as voltage references for any other device in the application.

MODE

PIN

MODE

FUNCTION

COMMENTS

AGND

Full external

external

REFT

=

external

REFB

=

On-chip reference generator and reference buffer are

not used.

AVDD

Top/Bottom

()

2

REFBS

REFTS

AVDD

REFTF

−

+

=

()

2

REFBS

REFTS

AVDD

REFBF

−

−

=

On-chip reference generator is not used. Reference

buffer centers external reference voltages around

AVDD/2.

Table 2 WM8200 Reference Generation Modes

and zero scale by