AT45DB161E datasheet(40/80 Pages) DIALOG

40 / 80 page

AT45DB161E

DS-AT45DB161E–8782N–03-2021

The Ultra-Deep Power-Down command is ignored if an internally self-timed operation such as a program or erase

cycle is in progress. The Ultra-Deep Power-Down command must be reissued after the internally self-timed

operation has been completed in order for the device to enter the Ultra-Deep Power-Down mode.

Figure 11-3. Ultra-Deep Power-Down Timing

11.3 Exit Ultra-Deep Power-Down

To exit from the Ultra-Deep Power-Down mode, the CS pin must be pulsed by asserting the CS pin, waiting the

minimum necessary tCSLU time, and then deasserting the CS pin again. To facilitate simple software development,

a dummy byte opcode can also be entered while the CS pin is being pulsed just as in a normal operation like the

Program Suspend operation; the dummy byte opcode is ignored by the device in this case. After the CS pin has

been deasserted, the device exits from the Ultra-Deep Power-Down mode and return to the standby mode within a

maximum time of tXUDPD. If the CS pin is reasserted before the tXUDPD time has elapsed in an attempt to start a new

operation, then that operation is ignored and nothing is performed. The system must wait for the device to return to

the standby mode before normal command operations such as Continuous Array Read can be resumed.

Since the contents of the SRAM buffers cannot be maintained while in the Ultra-Deep Power-Down mode, the

SRAM buffers contains undefined data when the device returns to the standby mode.

Figure 11-4. Exit Ultra-Deep Power-Down

SCK

MSB

ICC

Opcode

High-impedance

Ultra-Deep Power-Down Mode Current

Active Current

Standby Mode Current

tEUDPD

1111001

ICC

High-impedance

Ultra-Deep Power-Down Mode Current

Active Current

Standby Mode Current

tXUDPD

tCSLU

AT45DB161E Datasheet(PDF) 40 Page - Dialog Semiconductor