AT45DB161E datasheet(41/80 Pages) DIALOG

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AT45DB161E

DS-AT45DB161E–8782N–03-2021

Buffer and Page Size Configuration

The memory array of DataFlash devices is actually larger than other Serial Flash devices in that extra user-

accessible bytes are provided in each page of the memory array. For the AT45DB161E, there are an extra 16

bytes of memory in each page for a total of an extra 64 kB (512 kbits) of user-accessible memory. Therefore, the

device density is actually 16.5 Mbits instead of 16 Mbits.

Some designers, however, might not want to take advantage of this extra memory and instead architect their

software to operate on a “power of 2” binary, logical addressing scheme. To allow this, the DataFlash can be

configured so that the buffer and page sizes are 512 bytes instead of the standard 528 bytes. Also, the

configuration of the buffer and page sizes is reversible and can be changed from 528 bytes to 512 bytes or from

512 bytes to 528 bytes. The configured setting is stored in an internal nonvolatile register so that the buffer and

page size configuration is not affected by power cycles. The nonvolatile register has a limit of 10,000

erase/program cycles; therefore, be careful not to switch between the size options more than 10,000 times.

Devices are initially shipped from Adesto with the buffer and page sizes set to 528 bytes. Devices can be ordered

from Adesto pre-configured for the “power of 2” binary size of 512 bytes. For details, see Section 28, Ordering

Information, on page 70.

To configure the device for “power of 2” binary page size (512 bytes), a four-byte opcode sequence of 3Dh, 2Ah,

80h, and A6h must be clocked into the device. After the last bit of the opcode sequence has been clocked in, the

CS pin must be deasserted to initiate the internally self-timed configuration process and nonvolatile register

program cycle. Programming of the nonvolatile register takes a time of tEP, during which time the RDY/BUSY bit in

the Status Register indicates that the device is busy. The device does not need to be power cycled after the

configuration process and register program cycle in order for the buffer and page size to be configured to 512

bytes.

To configure the device for standard DataFlash page size (528 bytes), a four-byte opcode sequence of 3Dh, 2Ah,

80h, and A7h must be clocked into the device. After the last bit of the opcode sequence has been clocked in, the

CS pin must be deasserted to initial the internally self-timed configuration process and nonvolatile register program

cycle. Programming of the nonvolatile register takes a time of tEP, during which time the RDY/BUSY bit in the

Status Register indicates that the device is busy. The device does not need to be power cycled after the

configuration process and register program cycle in order for the buffer and page size to be configured to 528

bytes.

Table 12-1. Buffer and Page Size Configuration Commands

Figure 12-1. Buffer and Page Size Configuration

Command

Byte 1

Byte 2

Byte 3

Byte 4

“Power of 2” binary page size (512 bytes)

3Dh

2Ah

80h

A6h

DataFlash page size (528 bytes)

3Dh

2Ah

80h

A7h

3Dh

2Ah

80h

Opcode

Byte 4

Each transition represents eight bits

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