BIT(S)

BIT REF.

DESCRIPTION

33-38

M[0]..M[5]

M counter control bits

Modulus = value +1

39

FBKPOL

External feedback polarity control bit. The PLL will lock to the falling

edge of EXTFBK when FBKPOL=1 and to the rising edge of EXTFBK

when FBKPOL=0.

40

DBLFREQ

Doubles modulus of dual-modulus prescaler (from 6/7 to 12/14).

41-44

A[0]..A[3]

Controls A counter. When set to zero, modulus=7. Otherwise,

modulus=7 for “value” underflows of the prescaler, and modulus=6

thereafter until M counter underflows.

45

RESERVED

Set to zero.

46

LOADEN~

Load clock divider enable (active low). When set to logic 1, the LOAD

and LD/N2 outputs will cease toggling.

47

SKEW-

Differential output duty factor adjust.

48

SKEW+

49-55

R[0]..R[6]

Reference divider modulus control bits

Modulus = value + 1

56

REFPOL

PLL locks to the rising edge of XTAL1 input when REFPOL=1 and to

the falling edge of XTAL1 when REFPOL=0.

SKEW+

SKEW-

0

0

Default

0

1

100 ps

1

0

100 ps

1

1

Do not use

ICS1562B

13